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ez-otg? programmable usb on-the-go host/peripheral controller CY7C67200 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08014 rev. *f revised june 27, 2006 1.0 ez-otg features ? single-chip programmable usb dual role (host/peripheral) controller with two configurable serial interface engines (sie?s) and two usb ports ? supports usb otg protocol ? on-chip 48 mhz 16-bit processor with dynamically switchable clock speed ? configurable io block supports a variety of io options or up to 25 bits of general purpose io (gpio) ? 4k 16 internal mask rom contains built-in bios that supports a communication-ready state with access to i 2 c? eeprom interface, external rom, uart, or usb ? 8k x 16 internal ram for code and data buffering ? 16-bit parallel host port interface (hpi) with dma/mailbox data path for an external processor to directly access all on- chip memory and control on-chip sie?s ? fast serial port supports from 9600 baud to 2.0m baud ? spi supports both master and slave ? supports 12 mhz external crystal or clock ? 2.7v to 3.6v power supply voltage ? package option ? 48-pin fbga 2.0 typical applications ez-otg is a very powerful and flexible dual-role usb controller that supports a wide variety of applications. it is primarily intended to enable usb otg capability in applica- tions such as: ? cellular phones ? pda?s and pocket pc?s ? video and digital still cameras ? mp3 players ? mass storage devices timer 0 timer 1 watchdog control 4kx16 rom bios 8kx16 ram cy16 16-bit risc core sie1 usb-a sie2 usb-a otg host/ peripheral usb ports d+,d- d+,d- uart i/f hss i/f i2c eeprom i/f hpi i/f spi i/f nreset CY7C67200 gpio [24:0] pll x1 x2 gpio shared input/output pins vbus, id mobile power booster block diagram CY7C67200
CY7C67200 document #: 38-08014 rev. *f page 2 of 82 3.0 introduction ez-otg? (CY7C67200) is cypress semiconductor?s first usb on-the-go (otg) host/peripheral controller. ez-otg is designed to easily interface to most high-performance cpus to add usb host functionality. ez-otg has its own 16-bit risc processor to act as a coprocessor or operate in standalone mode. ez-otg also has a programmable io interface block allowing a wide range of interface options. 4.0 processor core functional overview an overview of the processo r core components are presented in this section. 4.1 processor ez-otg has a general purpose 16-bit embedded risc processor that runs at 48 mhz. 4.2 clocking ez-otg requires a 12 mhz source for clocking. either an external crystal or ttl-level oscillator may be used. ez-otg has an internal pll that produces a 48 mhz internal clock from the 12 mhz source. 4.3 memory ez-otg has a built-in 4k 16 masked rom and an 8k 16 internal ram. the masked rom contains the ez-otg bios. the internal ram can be used for program code or data. 4.4 interrupts ez-otg provides 128 interrupt vectors. the first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts. 4.5 general timers and watchdog timer ez-otg has two built-in programmable timers and a watchdog timer. all three timers can generate an interrupt to the ez-otg. 4.6 power management ez-otg has one main power-saving mode, sleep. sleep mode pauses all operations and provides the lowest power state. 5.0 interface descriptions ez-otg has a variety of interface options for connectivity, with several interface options available. see table 5-1 to under- stand how the interfaces share pins and can coexist. below are some general guidelines: ? i2c eeprom and otg do not c onflict with any interfaces ? hpi is mutually exclusive to hss, spi, and uart table 5-1. interface options for gpio pins gpio pins hpi hss spi uart i2c otg gpio31 scl/sda gpio30 scl/sda gpio29 otgid gpio24 int gpio23 nrd gpio22 nwr gpio21 ncs gpio20 a1 gpio19 a0 gpio15 d15 cts gpio14 d14 rts gpio13 d13 rxd gpio12 d12 txd gpio11 d11 mosi gpio10 d10 sck gpio9 d9 nssi gpio8 d8 miso gpio7 d7 tx gpio6 d6 rx gpio5 d5 gpio4 d4 gpio3 d3 gpio2 d2 gpio1 d1 gpio0 d0
CY7C67200 document #: 38-08014 rev. *f page 3 of 82 5.1 usb interface ez-otg has two built-in host/peripheral sie?s that each have a single usb transceiver, meeting the usb 2.0 specification requirements for full- and low-speed (high-speed is not sup- ported). in host mode, ez-o tg supports two downstream ports; each supports control, interrupt, bulk, and isochronous transfers. in peripheral mode, ez-otg supports one periph- eral port with eight endpoints for each of the two sie?s. end- point 0 is dedicated as the control endpoint and only supports control transfers. endpoints 1 though 7 support interrupt, bulk (up to 64 bytes per packet), or isochronous transfers (up to 1023 bytes per packet size). ez-otg also supports a combi- nation of host and peripheral ports simultaneously as shown in table 5-2 . 5.1.1 usb features ? usb 2.0 compatible for full- and low-speed ? up to two downstream usb host ports ? up to two upstream usb peripheral ports ? configurable endpoint buffers (pointer and length), must reside in internal ram ? up to eight available peripheral endpoints (1 control endpoint) ? supports control, interrupt, bulk, and isochronous transfers ? internal dma channels for each endpoint ? internal pull up and pull down resistors ? internal series terminatio n resistors on usb data lines 5.1.2 usb pins 5.2 otg interface ez-otg has one usb port that is compatible with the usb on-the-go supplement to the u sb 2.0 specification. the usb otg port has various hardware features to support session request protocol (srp) and host negotiation protocol (hnp). otg is only supported on usb port 1a. 5.2.1 otg features ? internal charge pump to supply and control vbus ? vbus valid status (above 4.4v) ? vbus status for 2.4v< vbus <0.8v ? id pin status ? switchable 2 kohm internal discharge resistor on vbus ? switchable 500 ohm internal pull up resistor on vbus ? individually switchable internal pull up and pull down resistors on the usb data lines 5.2.2 otg pins 5.3 general purpose io interface ez-otg has up to 25 gpio signals available. several other optional interfaces use gpio pins as well and may reduce the overall number of available gpio?s. 5.3.1 gpio description all inputs are sampled asynchronously with state changes oc- curring at a rate of up to two 48 mhz clock cycles. gpio pins are latched directly into registers, a single flip-flop. 5.3.2 unused pin descriptions unused usb pins must be tri-stated with the d+ line pulled high through the internal pull up resistor and the d- line pulled low through the internal pull down resistor. unused gpio pins must be configured as outputs and driven low. 5.4 uart interface ez-otg has a built-in uart interface. the uart interface supports data rates from 900 to 115.2k baud. it can be used as a development port or for other interface requirements. the uart interface is exposed through gpio pins. table 5-2. usb port configuration options port configurations port 1a port 2a otg otg ? otg + 1 host otg host otg + 1 peripheral otg peripheral 1 host + 1 peripheral host peripheral 1 host + 1 peripheral peripheral host 2 hosts host host 1 host host ? 1 host ? host 2 peripherals peripheral peripheral 1 peripheral peripheral ? 1 peripheral ? peripheral table 5-3. usb interface pins pin name pin number dm1a f2 dp1a e3 dm2a c2 dp2a d3 table 5-4. otg interface pins pin name pin number dm1a f2 dp1a e3 otgvbus c1 otgid f4 cswitcha d1 cswitchb d2
CY7C67200 document #: 38-08014 rev. *f page 4 of 82 5.4.1 uart features ? supports baud rates of 900 to 115.2k ?8-n-1 5.4.2 uart pins 5.5 i 2 c eeprom interface ez-otg provides a master only i2c interface for external se- rial eeprom?s. the serial eeprom can be used to store ap- plication specific code and data. this i2c interface is only to be used for loading code out of eeprom, it is not a general i2c interface. the i2c eeprom interface is a bios imple- mentation and is exposed through gpio pins. refer to the bios documentation for additional details on this interface. 5.5.1 i 2 c eeprom features ? supports eeprom?s up to 64 kb (512k bit) ? auto-detection of eeprom size 5.5.2 i 2 c eeprom pins 5.6 serial peripheral interface ez-otg provides an spi interface for added connectivity. ez- otg may be configured as either an spi master or spi slave. the spi interface can be exposed through gpio pins or the external memory port. 5.6.1 spi features ? master or slave mode operation ? dma block transfer and pio byte transfer modes ? full duplex or half duplex data communication ? 8-byte receive fifo and 8-byte transmit fifo ? selectable master spi clock rates from 250 khz to 12 mhz ? selectable master spi clock phase and polarity ? slave spi signaling synchronization and filtering ? slave spi clock rates up to 2 mhz ? maskable interrupts for block and byte transfer modes ? individual bit transfer for non-byte aligned serial communi- cation in pio mode ? programmable delay timing for the active/in-active master spi clock ? auto or manual control for ma ster mode slave select signal ? complete access to internal memory 5.6.2 spi pins the spi port has a few different pin location options as shown in table 5-7 . the pin location is selectable via the gpio con- trol register [0xc006]. 5.7 high-speed serial interface ez-otg provides an hss interface. the hss interface is a programmable serial connection with baud rate from 9600 baud to 2m baud. the hss interface supports both byte and block mode operations as well as hardware and software handshaking. complete control of ez-otg can be accom- plished through this interface via an extensible api and com- munication protocol. the hss interface can be exposed through gpio pins or the external memory port. 5.7.1 hss features ? 8-bit, no parity code ? programmable baud rate from 9600 baud to 2m baud ? selectable 1- or 2-stop bit on transmit ? programmable inter-character gap timing for block transmit ? 8-byte receive fifo ? glitch filter on receive ? block mode transfer directly to/from ez-otg internal memory (dma transfer) ? selectable cts/rts hardware signal handshake protocol ? selectable xon/xoff software handshake protocol ? programmable receive interrupt, block transfer done interrupts ? complete access to internal memory 5.7.2 hss pins table 5-5. uart interface pins pin name pin number tx b5 rx b4 table 5-6. i 2 c eeprom interface pins pin name pin number small eeprom sck h3 sda f3 large eeprom sck f3 sda h3 table 5-7. spi interface pins pin name pin number nssi f6 or c6 sck d5 mosi d4 miso c5 table 5-8. hss interface pins pin name pin number cts f6 rts e4 rx e5 tx e6
CY7C67200 document #: 38-08014 rev. *f page 5 of 82 5.8 host port interface (hpi) ez-otg has an hpi interface. the hpi interface provides dma access to the ez-otg internal memory by an external host, plus a bidirectional mailbox register for supporting high- level communication protocols. this port is designed to be the primary high-speed connection to a host processor. complete control of ez-otg can be accomplished through this interface via an extensible api and comm unication protocol. other than the hardware communication protocols, a host processor has identical control over ez-host whether connecting to the hpi or hss port. the hpi interface is exposed through gpio pins. note it should be noted that for up to 3 ms after bios starts executing, gpio[24:19] and gpio[15:8] will be driven as outputs for a test mode. if these pins need to be used as inputs, a series resistor is required (10 ohm - 48 ohm is recom- mended). refer to bios documentation for addition details. see ?reset pin? on page 9. 5.8.1 hpi features ? 16-bit data bus interface ? 16 mb/s throughput ? auto-increment of address pointer for fast block mode transfers ? direct memory access (dma) to internal memory ? bidirectional mailbox register ? byte swapping ? complete access to internal memory ? complete control of sie?s through hpi ? dedicated hpi status register 5.8.2 hpi pins the two hpi address pins are used to address one of four possible hpi port registers as shown in table 5-10 below. 5.9 charge pump interface vbus for the usb on-the-go (otg) port can be produced by ez-otg using its built-in charge pump and some external components. the circuit connections should look similar to the diagram below. component details: ? d1 and d2: schottky diodes wit h a current rating greater than 60 ma. ? c1: ceramic capacitor with a capacitance of 0.1 f. ? c2: capacitor value must be no more that 6.5 f since that is the maximum capacitance allowed by the usb otg specification for a dual-role device. the minimum value of c2 is 1 f. there are no restrictions on the type of capacitor for c2. if the vbus charge pump circuit is not to be used, cswitcha, cswitchb, and otgvbus can be left uncon- nected. notes: 1. hpi_int is for the outgoing mailbox interrupt. 2. hpi strobes are negative logic sampled on rising edge. table 5-9. hpi interface pins [1, 2] pin name pin number int h4 nrd g4 nwr h5 ncs g5 a1 h6 a0 f5 d15 f6 d14 e4 d13 e5 d12 e6 d11 d4 d10 d5 d9 c6 d8 c5 d7 b5 d6 b4 d5 c4 d4 b3 d3 a3 d2 c3 d1 a2 d0 b2 table 5-10. hpi addressing hpi a[1:0] a1 a0 hpi data 0 0 hpi mailbox 0 1 hpi address 1 0 hpi status 1 1 figure 5-1. charge pump table 5-9. hpi interface pins [1, 2] (continued) pin name pin number cswitcha CY7C67200 cswitchb otgvbus d1 d2 c1 c2 vbus
CY7C67200 document #: 38-08014 rev. *f page 6 of 82 5.9.1 charge pump features ? meets otg supplement requirements, see table 14-2, ?dc characteristics: charge pump,? on page 70. 5.9.2 charge pump pins 5.10 booster interface ez-otg has an on-chip power booster circuit for use with power supplies that range between 2.7v and 3.6v. the booster circuit boosts the power to 3.3v nominal to supply power for the entire chip. the booster circuit requires an external inductor, diode, and capacitor. during power down mode, the circuit is disabled to save power. figure 5-2 shows how to connect the booster circuit. component details: ? l1: inductor with inductance of 10 h and a current rating of at least 250 ma ? d1: schottky diode with a current rating of at least 250 ma ? c1: tantalum or ceramic capacitor with a capacitance of at least 2.2 f figure 5-3 shows how to connect the power supply when the booster circuit is not being used. 5.10.1 booster pins 5.11 crystal interface the recommended crystal circuit to be used with ez-otg is shown in figure 5-4 . if an oscillator is used instead of a crystal circuit, connect it to xtalin and leave xtalout uncon- nected. for further information on the crystal requirements, see table 13-1, ?crystal requirements,? on page 69. table 5-11. charge pump interface pins pin name pin number otgvbus c1 cswitcha d1 cswitchb d2 figure 5-2. power supply connection with booster boostvcc vswitch vcc avcc c1 d1 l1 3.3v 2.7v to 3.6v power supply figure 5-3. power supply connection without booster table 5-12. charge pump interface pins pin name pin number boostvcc f1 vswitch e2 figure 5-4. crystal interface boostvcc vswitch vcc avcc 3.0v to 3.6v power supply y1 c1 = 22 pf c2 = 22 pf CY7C67200 xtalin xtalout 12mhz parallel resonant fundamental mode 500uw 20-33pf 5%
CY7C67200 document #: 38-08014 rev. *f page 7 of 82 5.11.1 crystal pins 5.12 boot configuration interface ez-otg can boot into any one of four modes. the mode it boots into is determined by the ttl voltage level of gpio[31:30] at the time nreset is deasserted. table 5-14 shows the different boot pin combinations possible. after a reset pin event occurs, the bios bootup procedure executes for up to 3 ms. gpio[31:30] are sampled by the bios during bootup only. after bootup these pins are available to the appli- cation as gpio?s. gpio[31:30] must be pulled high or low as needed using re- sistors tied to vcc or gnd with resistor values between 5k ohm and 15k ohm. gpio[31:30] mu st not be tied directly to vcc or gnd. note that in standalone mode, the pull ups on those two pins are used for the serial i2c eeprom (if imple- mented). the resistors used for these pull ups must conform to the serial eeprom manufacturer's requirements. if any mode other then standalo ne is chosen, ez-otg will be in coprocessor mode. the device will power up with the appro- priate communication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. see the bios documentation for greater detail on the boot process. 5.13 operational modes there are two modes of operation: coprocessor and standalone. 5.13.1 coprocessor mode ez-otg can act as a coprocessor to an external host processor. in this mode, an external host processor drives ez- otg and is the main processor rather then ez-otg?s own 16- bit internal cpu. an external host processor may interface to ez-otg through one of the following three interfaces in copro- cessor mode: ? hpi mode, a 16-bit parallel in terface with up to 16 mbytes transfer rate ? hss mode, a serial interface with up to 2m baud transfer rate ? spi mode, a serial interface with up to 2 mbits/s transfer rate. at bootup gpio[31:30] determine which of these three inter- faces are used for coprocessor mode. refer to table 5-14 for details. bootloading begins from the selected interface after por + 3 ms of bios bootup. 5.13.2 standalone mode in standalone mode, there is no external processor connected to ez-otg. instead, ez-otg?s own internal 16-bit cpu is the main processor and firmware is typically downloaded from an eeprom. optionally, firmware may also be downloaded via usb. refer to table 5-14 for booting into standalone mode. after booting into standalone mo de (gpio[31:30] = ?11?), the following pins are affected: ? gpio[31:30] are configured as output pins to examine the eeprom contents. ? gpio[28:27] are enabled for debug uart mode. ? gpio[29] is configured as otgid for otg applications on port1a. ? if otgid is logic 1 then port1a (otg) is configured as a usb peripheral. ? if otgid is logic 0 then port1a (otg) is configured as a usb host. ? ports 1b, 2a, and 2b default as usb peripheral ports. ? all other pins remain input pins. table 5-13. crystal pins pin name pin number xtalin g3 xtalout g2 table 5-14. boot configuration interface gpio31 (pin 39) gpio30 (pin 40) boot mode 0 0 host port interface (hpi) 0 1 high speed serial (hss) 1 0 serial peripheral interface (spi, slave mode) 1 1 i2c eeprom (standalone mode)
CY7C67200 document #: 38-08014 rev. *f page 8 of 82 5.13.2.1 minimum hardware requirements for standalone mode ? peripheral only 6.0 power savings and reset description the ez-otg modes and reset conditions are described in this section. 6.1 power savings mode description ez-otg has one main power savings mode, sleep. for de- tailed information on sleep mode, see section 6.2. sleep mode is used for usb applications to support usb sus- pend and non usb applications as the main chip power down mode. in addition, ez-otg is capable of slowing down the cpu clock speed through the cpu speed r egister [0xc008] without af- fecting other peripheral timing. reducing the cpu clock speed from 48 mhz to 24 mhz reduces the overall current draw by around 8 ma while reducing it from 48 mhz to 3 mhz reduces the overall current draw by approximately 15 ma. 6.2 sleep sleep mode is the main chip power down mode and is also used for usb suspend. sleep mode is entered by setting the sleep enable (bit 1) of the power control register [0xc00a]. during sleep mode (usb suspend) the following events and states are true: ? gpio pins maintain their configuration during sleep (in suspend). ? external memory address pins are driven low. ? xtalout is turned off. ? internal pll is turned off. ? firmware must disable the charge pump (otg control register [0xc098]) causing otgvbus to drop below 0.2v. otherwise otgvbus will only drop to v cc ? (2 schottky diode drops). ? booster circuit is turned off. ? usb transceivers is turned off. ? cpu suspends until a programmable wakeup event. 6.3 external (remote) wakeup source there are several possible events available to wake ez-otg from sleep mode as shown in table 6-1 . these may also be used as remote wakeup options for usb applications. see ?power control register [0xc00a] [r/w]? on page 13. upon wakeup, code begins executing within 200 ms, the time it takes the pll to stabilize. figure 5-5. minimum standalone hardware configuration ? peripheral only ez-otg CY7C67200 gpio[30] gpio[31] scl* sda* 10k bootstrap options bootloading firmware *bootloading begins after por + 3ms bios bootup vcc 10k vcc a2 gnd a0 a1 scl sda vcc wp vcc up to 64k x8 eeprom *gpio[31:30] 31 30 up to 2k x8 scl sda >2k x8 to 64k x8 sda scl int. 16k x8 code / data xout xin 12mhz 22pf 22pf nreset reset logic * parallel resonant fundamental mode 500uw 20-33pf 5% vcc, avcc, boostvcc vreg dminus dplus standard-b or mini-b d+ vbus gnd d- shield reserved gnd, agnd, boostgnd
CY7C67200 document #: 38-08014 rev. *f page 9 of 82 6.4 power-on reset (por) description the length of the power-on-reset event can be defined by (vcc ramp to valid) + (crystal start up). a typical application might utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively. 6.5 reset pin the reset pin is active low and requires a minimum pulse duration of sixteen 12-mhz clock cycles (1.3 ms). a reset event restores all registers to their default por settings. code execution then begins 200 ms later at 0xff00 with an imme- diate jump to 0xe000, the start of bios. note it should be noted that for up to 3 ms after bios starts executing, gpio[24:19] and gpio[ 15:8] will be driven as out- puts for a test mode. if these pins need to be used as inputs, a series resistor is required (10 ohm - 48 ohm is recommend- ed). refer to bios documentation for addition details. 6.6 usb reset a usb reset affects registers 0xc090 and 0xc0b0, all other registers remain unchanged. 7.0 memory map memory map information is presented in this section. 7.1 mapping the ez-otg has just over 24 kb of addressable memory mapped from 0x0000 to 0xffff. this 24 kb contains both program and data space and is byte addressable. figure 7-1 . shows the various memory region address locations. 7.2 internal memory of the internal memory, 15 kb is allocated for user?s program and data code. the lower memory space from 0x0000 to 0x04a2 is reserved for interru pt vectors, general purpose registers, usb control register s, the stack, and other bios variables. the upper internal memory space contains ez-otg control registers from 0xc000 to 0xc0ff and the bios rom itself from 0xe000 to 0xffff . for more information on the reserved lower memory or t he bios rom, refer to the programmers documentation and the bios documentation. during development with the ez-o tg toolset, the lower area of user's space (0x04a4 to 0x1000) should be left available to load the gdb stub. the gdb stub is required to allow the toolset debug access into ez-otg. notes: 3. read data will be discarded (dummy data). 4. hpi_int will assert on a usb resume.registers table 6-1. wakeup sources [3, 4] wakeup source (if enabled) event usb resume d+/d- signaling otgvbus level otgid any edge hpi read hss read spi read irq0 (gpio 24) any edge hw int's sw int's 0x0000 - 0x00ff primary registers swap registers usb registers hpi int / mailbox slave setup packet bios user space ~15k internal memory control registers 0x0100 - 0x011f 0x0120 - 0x013f 0x0140 - 0x0148 0x014a - 0x01ff 0x0200- 0x02ff lcp variables 0x0300- 0x030f bios stack 0x0310- 0x03ff usb slave & otg 0x0400- 0x04a2 0x04a4- 0x3fff 0xc000- 0xc0ff 0xe000- 0xffff figure 7-1. memory map
CY7C67200 document #: 38-08014 rev. *f page 10 of 82 8.0 registers some registers have different functions for a read vs. a write access or usb host vs. u sb device mode. therefore, registers of this type will have multiple definitions for the same address. the default register values listed in this data sheet may get altered to some other value during bios initialization. refer to the bios documentation for register initialization information. 8.1 processor control registers there are eight registers dedicated to general processor control. each of these registers is covered in this section and is summarized in figure 8-1 . 8.1.1 cpu flags register [0xc000] [r] figure 8-2. cpu flags register register description the cpu flags register is a read only register that gives processor flags status. global interrupt enable (bit 4) the global interrupt enable bit indicates if the global inter- rupts are enabled. 1: enabled 0: disabled negative flag (bit 3) the negative flag bit indicates if an arithmetic operation results in a negative answer. 1: ms result bit is ?1? 0: ms result bit is not ?1? overflow flag (bit 2) the overflow flag bit indicates if an overflow condition has occurred. an overflow condition can occur if an arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction. 1: overflow occurred 0: overflow did not occur carry flag (bit 1) the carry flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction. 1: carry/borrow occurred 0: carry/borrow did not occur zero flag (bit 0) the zero flag bit indicates if an instruction execution resulted in a ?0?. 1: zero occurred 0: zero did not occur figure 8-1. processor control registers register name address r/w cpu flags register 0xc000 r register bank register 0xc002 r/w hardware revision register 0xc004 r cpu speed register 0xc008 r/w power control register 0xc00a r/w interrupt enable register 0xc00e r/w breakpoint register 0xc014 r/w usb diagnostic register 0xc03c w bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved global interrupt enable negative flag overflow flag carry flag zero flag read/write - - - r r r r r default 0 0 0 x x x x x
CY7C67200 document #: 38-08014 rev. *f page 11 of 82 8.1.2 bank register [0xc002] [r/w] figure 8-3. bank register register description the bank register maps registers r0?r15 into ram. the eleven msbs of this register are used as a base address for registers r0?r15. a register address is automatically generated by: a. shifting the four lsbs of the register address left by 1 b. oring the four shifted bits of the register address with the 12 msbs of the bank register c. forcing the lsb to zero for example, if the bank register is left at its default value of 0x0100, and r2 is read, then the physical address 0x0102 will be read. see ta ble 8-1 for details . address (bits [15:4]) the address field is used as a base address for all register addresses to start from. reserved all reserved bits must be written as ?0?. 8.1.3 hardware revision register [0xc004] [r] figure 8-4. revision register register description the hardware revision register is a read only register that indicates the silicon revision number. the first silicon revision is represented by 0x0101. this number is increased by one for each new silicon revision. revision (bits [15:0]) the revision field contains the silicon revision number. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field ...address reserved read/write r/w r/w r/w - - - - - default 0 0 0 x x x x x table 8-1. bank register example register hex value binary value bank 0x0100 0000 0001 0000 0000 r14 0x000e << 1 = 0x001c 0000 0000 0001 1100 ram location 0x011c 0000 0001 0001 1100 bit # 15 14 13 12 11 10 9 8 field revision... read/write r r r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...revision read/write r r r r r r r r default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 12 of 82 8.1.4 cpu speed register [0xc008] [r/w] figure 8-5. cpu speed register register description the cpu speed register allows the processor to operate at a user selected speed. this register on ly affects the cpu, all other peripheral timing is still based on the 48 -mhz system clock (unless otherwise noted). cpu speed (bits[3:0]) the cpu speed field is a divisor that selects the operating speed of the processor as defined in table 8-2 . reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved cpu speed read/write - - - - r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 table 8-2. cpu speed definition cpu speed [3:0] processor speed 0000 48 mhz/1 0001 48 mhz/2 0010 48 mhz/3 0011 48 mhz/4 0100 48 mhz/5 0101 48 mhz/6 0110 48 mhz/7 0111 48 mhz/8 1000 48 mhz/9 1001 48 mhz/10 1010 48 mhz/11 1011 48 mhz/12 1100 48 mhz/13 1101 48 mhz/14 1110 48 mhz/15 1111 48 mhz/16
CY7C67200 document #: 38-08014 rev. *f page 13 of 82 8.1.5 power control register [0xc00a] [r/w] figure 8-6. power control register register description the power control register controls the power-down and wakeup options. either the sleep mode or the halt mode options can be selected. all other writable bits in this register can be used as a wakeup source while in sleep mode. host/device 2 wake enable (bit 14) the host/device 2 wake enable bit enables or disables a wakeup condition to occur on an host/device 2 transition. this wake up from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 2 transition. 0: disable wakeup on host/device 2 transition. host/device 1 wake enable (bit 12) the host/device 1 wake enable bit enables or disables a wakeup condition to occur on an host/device 1 transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 1 transition 0: disable wakeup on host/device 1 transition otg wake enable (bit 11) the otg wake enable bit enables or disables a wakeup condition to occur on either an otg vbus_valid or otg id transition (irq20). 1: enable wakeup on otg vbus valid or otg id transition 0: disable wakeup on otg vbus valid or otg id transition hss wake enable (bit 9) the hss wake enable bit enables or disables a wakeup condition to occur on an hss rx serial input transition. the processor may take several hundreds of microseconds before being operational after wakeup. therefore, the incoming data byte that causes the wakeup will be discarded. 1: enable wakeup on hss rx serial input transition 0: disable wakeup on hss rx serial input transition spi wake enable (bit 8) the spi wake enable bit enables or disables a wakeup condition to occur on a falling spi_nss input transition. the processor may take several hundreds of microseconds before being operational after wakeup. therefore, the incoming data byte that causes the wakeup will be discarded. 1: enable wakeup on falling spi nss input transition 0: disable spi_nss interrupt hpi wake enable (bit 7) the hpi wake enable bit enables or disables a wakeup condition to occur on an hpi interface read. 1: enable wakeup on hpi interface read 0: disable wakeup on hpi interface read gpi wake enable (bit 4) the gpi wake enable bit enables or disables a wakeup condition to occur on a gpio(25:24) transition. 1: enable wakeup on gp io(25:24) transition 0: disable wakeup on gpio(25:24) transition boost 3v ok (bit 2) the boost 3v ok bit is a read only bit that returns the status of the otg boost circuit. 1: boost circuit not ok and internal voltage rails are below 3.0v 0: boost circuit ok and internal voltage rails are at or above 3.0v sleep enable (bit 1) setting this bit to ?1? immediately init iates sleep mode. while in sleep mode, the entire chip is paused achieving the lowest standby power state. all operat ions are paused, the internal clock is stopped, the booster circuit and otg vbus charge pump are all powered down, and the usb transceivers are powered down. all counters and timers are paused but will retain their values. sleep mode exits by any activity selected in this register. when sleep mode ends, instruction execution resumes within 0.5 ms. 1: enable sleep mode 0: no function halt enable (bit 0) setting this bit to ?1? immediately initiates halt mode. while in halt mode, only the cpu is stopped. the internal clock still runs and all peripherals still operate, including the usb engines. the power savings using halt in most cases will be bit # 15 14 13 12 11 10 9 8 field reserved host/device 2 wake enable reserved host/device 1 wake enable otg wake enable reserved hss wake enable spi wake enable read/write - r/w - r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable read/write r/w - - r/w - r r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 14 of 82 minimal, but in applications t hat are very cpu intensive the incremental savings may provide some benefit. the halt state is exited when any enabled interrupt is triggered. upon exiting the halt state, one or two instructions immediately following the halt instruction may get executed before the waking interrupt is serviced (you may want to follow the halt instruction with two nops). 1: enable halt mode 0: no function reserved all reserved bits must be written as ?0?. 8.1.6 interrupt enable register [0xc00e] [r/w] figure 8-7. interrupt enable register register description the interrupt enable register allows control of the hardware interrupt vectors. otg interrupt enable (bit 12) the otg interrupt enable bit enables or disables the otg id/otg4.4v valid hardware interrupt. 1: enable otg interrupt 0: disable otg interrupt spi interrupt enable (bit 11) the spi interrupt enable bit enables or disables the following three spi hardware interrupts: spi tx, spi rx, and spi dma block done. 1: enable spi interrupt 0: disable spi interrupt host/device 2 interrupt enable (bit 9) the host/device 2 interrupt enable bit enables or disables all of the following host/device 2 hardware interrupts: host 2 usb done, host 2 usb sof/eop, host 2 wakeup/insert/remove, device 2 reset, device 2 sof/eop or wakeup from usb, device 2 endpoint n. 1: enable host 2 and device 2 interrupt 0: disable host 2 and device 2 interrupt host/device 1 interrupt enable (bit 8) the host/device 1 interrupt enable bit enables or disables all of the following host/device 1 hardware interrupts: host 1 usb done, host 1 usb sof/eop, host 1 wakeup/insert/remove, device 1 reset, device 1 sof/eop or wakeup from usb, device 1 endpoint n. 1: enable host 1 and device 1 interrupt 0: disable host 1 and device 1 interrupt hss interrupt enable (bit 7) the hss interrupt enable bit enables or disables the following high-speed serial interface hardware interrupts: hss block done, and hss rx full. 1: enable hss interrupt 0: disable hss interrupt in mailbox interrupt enable (bit 6) the in mailbox interrupt enable bit enables or disables the hpi: incoming mailbox hardware interrupt. 1: enable mbxi interrupt 0: disable mbxi interrupt out mailbox interrupt enable (bit 5) the out mailbox interrupt enable bit enables or disables the hpi: outgoing mailbox hardware interrupt. 1: enable mbxo interrupt 0: disable mbxo interrupt bit # 15 14 13 12 11 10 9 8 field reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable read/write - - - r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable read/write r/w r/w r/w - r/w r/w r/w r/w default 0 0 0 1 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 15 of 82 uart interrupt enable (bit 3) the uart interrupt enable bit enables or disables the following uart hardware interrupts: uart tx, and uart rx. 1: enable uart interrupt 0: disable uart interrupt gpio interrupt enable (bit 2) the gpio interrupt enable bit enables or disables the general purpose io pins interrupt (see the gpio control register). when gpio bit is reset, all pending gpio interrupts are also cleared. 1: enable gpio interrupt 0: disable gpio interrupt timer 1 interrupt enable (bit 1) the timer 1 interrupt enable bit enables or disables the timer1 interrupt enable. when th is bit is reset, all pending timer 1 interrupts are cleared. 1: enable tm1interrupt 0: disable tm1 interrupt timer 0 interrupt enable (bit 0) the timer 0 interrupt enable bit enables or disables the timer0 interrupt enable. when th is bit is reset, all pending timer 0 interrupts are cleared. 1: enable tm0 interrupt 0: disable tm0 interrupt reserved all reserved bits must be written as ?0?. 8.1.7 breakpoint register [0xc014] [r/w] figure 8-8. breakpoint register register description the breakpoint register holds the breakpoint address. when t he program counter match this address, the int127 interrupt occurs. to clear this interrupt, a zero value must be written to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 16 of 82 8.1.8 usb diagnostic register [0xc03c] [r/w] figure 8-9. usb diagnostic register register description the usb diagnostic register provides control of diagnostic modes. it is intended for use by device characterization tests, not for normal operations. this register is read/write by the on-chip cpu but is write only via the hpi port. port 2a diagnostic enable (bit 15) the port 2a diagnostic enable bit enables or disables port 2a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions port 1a diagnostic enable (bit 15) the port 1a diagnostic enable bit enables or disables port 1a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions pull-down enable (bit 6) the pull-down enable bit enables or disables full-speed pull down resistors (pull down on both d+ and d?) for testing. 1: enable pull down resistors on both d+ and d? 0: disable pull down resistors on both d+ and d? ls pull-up enable (bit 5) the ls pull-up enable bit enables or disables a low-speed pull up resistor (pull up on d?) for testing. 1: enable low-speed pull up resistor on d? 0: pull-up resistor is not connected on d? fs pull-up enable (bit 4) the fs pull-up enable bit enables or disables a full-speed pull up resistor (pull up on d+) for testing. 1: enable full-speed pull up resistor on d+ 0: pull-up resistor is not connected on d+ force select (bits [2:0]) the force select field bit selects several different test condition states on the data lines (d+/d?). see table 8-3 for details. reserved all reserved bits must be written as ?0?. 8.2 timer registers there are three registers dedicated to timer operations. each of these registers are discussed in this section and are summarized in figure 8-10 . bit # 15 14 13 12 11 10 9 8 field reserved port 2a diagnostic enable reserved port 1a diagnostic enable reserved... read/write - r/w - r/w - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select read/write - r/w r/w r/w - r/w r/w r/w default 0 0 0 0 0 0 0 0 table 8-3. force select definition force select [2:0] data line state 1xx assert se0 01x toggle jk 001 assert j 000 assert k figure 8-10. timer registers register name address r/w watchdog timer register 0xc00c r/w timer 0 register 0xc010 r/w timer 1 register 0xc012 r/w
CY7C67200 document #: 38-08014 rev. *f page 17 of 82 8.2.1 watchdog timer register [0xc00c] [r/w] figure 8-11. watchdog timer register register description the watchdog timer register provide status and control over the watchdog timer. the watchdog timer can also interrupt the processor. timeout flag (bit 5) the timeout flag bit indicates if the watchdog timer has expired. the processor can read this bit after exiting a reset to determine if a watchdog time-out occurred. this bit is cleared on the next external hardware reset. 1: watchdog timer expired 0: watchdog timer did not expire period select (bits [4:3]) the period select field is defined in table 8-4 . if this time expires before the reset strobe bit is set, the internal processor gets reset. lock enable (bit 2) the lock enable bit does not allow any writes to this register until a reset. in doing so the watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the wdt enable bit is ignored). 1: watchdog timer permanently set 0: watchdog timer not permanently set wdt enable (bit 1) the wdt enable bit enables or disables the watchdog timer. 1: enable watchdog timer operation 0: disable watchdog timer operation reset strobe (bit 0) the reset strobe is a write-only bit that resets the watchdog timer count. it must be set to ?1? before the count expires to avoid a watchdog trigger 1: reset count reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved timeout flag period select lock enable wdt enable reset strobe read/write r/w r/w r/w r/w r/w r/w r/w w default 0 0 0 0 0 0 0 0 table 8-4. period select definition period select[4:3] wdt period value 00 1.4 ms 01 5.5 ms 10 22.0 ms 11 66.0 ms
CY7C67200 document #: 38-08014 rev. *f page 18 of 82 8.2.2 timer n register [r/w] ? timer 0 register 0xc010 ? timer 1 register 0xc012 figure 8-12. timer n register register description the timer n register sets the timer n count. both timer 0 and ti mer 1 decrement by one every 1 s clock tick. each can provide an interrupt to the cpu when the timer reaches zero. count (bits [15:0]) the count field sets the timer count. 8.3 general usb registers there is one set of register dedicated to gen eral usb control. this set consists of two identical registers, one for host/devic e port 1 and one for host/device port 2. this register set has functions for both usb host and usb peripheral options and is cove red in this section and summarized in figure 8-13 . usb host-only registers are covered in section 8.4 and usb device-only registers are covered in section 8.5. 8.3.1 usb n control register [r/w] ? usb 1 control register 0xc08a ? usb 2 control register 0xc0aa figure 8-14. usb n control register register description the usb n control register is used in both host and device mode. it monitors and controls the si e and the data lines of the usb ports. this register can be accessed by the hpi interface. bit # 15 14 13 12 11 10 9 8 field count... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 figure 8-13. usb registers register name address (sie1/sie2) r/w usb n control register 0xc08a/0xc0aa r/w bit # 15 14 13 12 11 10 9 8 field reserved port a d+ status port a d? status reserved loa mode select reserved read/write - - r r - r/w r/w - default x x x x 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field port a resistors enable reserved port a force d state suspend enable reserved port a sof/eop enable read/write r/w - - r/w r/w r/w - r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 19 of 82 port a d+ status (bit 13) the port a d+ status bit is a read only bit that indicates the value of data+ on port a. 1: d+ is high 0: d+ is low port a d? status (bit 12) the port a d? status bit is a read only bit that indicates the value of data? on port a. 1: d? is high 0: d? is low loa (bit 10) the loa bit selects the speed of port a. 1: port a is set to low speed mode 0: port a is set to full speed mode mode select (bit 9) the mode select bit sets the sie for host or device operation. when set for device operation only one usb port is supported. the active port is selected by the port select bit in the host n count register. 1: host mode 0: device mode port a resistors enable (bit 7) the port a resistors enable bit enables or disables the pull up/pull down resistors on po rt a. when enabled, the mode select bit and loa bit of this register sets the pull up/pull down resistors appropriately. when the mode select is set for host mode, the pull down resistors on the data lines (d+ and d?) are enabled. when the mode select is set for device mode, a single pull up resistor on either d+ or d?, determined by the loa bit, will be enabled. see table 8-5 for details. 1: enable pull up/pull down resistors 0: disable pull up/pull down resistors port a force d state (bits [4:3]) the port a force d state field controls the forcing state of the d+ d? data lines for port a. this field forces the state of t he port a data lines independent of the port select bit setting. see table 8-6 for details. suspend enable (bit 2) the suspend enable bit enables or disables the suspend featur e on both ports. when suspend is enabled the usb transceivers are powered down and can not transmit or received us b packets but can still monitor for a wakeup condition. 1: enable suspend 0: disable suspend port a sof/eop enable (bit 0) the port a sof/eop enable bit is only applicable in host mode. in device mode this bit must be wr itten as ?0?. in host mode thi s bit enables or disables sofs or eops fo r port a. either sofs or eops will be gen erated depending on the loa bit in the usb n control register when port a is active. 1: enable sofs or eops 0: disable sofs or eops reserved all reserved bits must be written as ?0?. table 8-5. usb data line pull up and pull down resistors l0a mode select port n resistors enable function x x 0 pull-up/pull-down on d+ and d? disabled x 1 1 pull-down on d+ and d? enabled 1 0 1 pull-up on usb d? enabled 0 0 1 pull-up on usb d+ enabled table 8-6. port a force d state port a force d state function msb lsb 0 0 normal operation 0 1 force usb reset, se0 state 1 0 force j-state. 1 1 force k-state.
CY7C67200 document #: 38-08014 rev. *f page 20 of 82 8.4 usb host only registers there are twelve sets of dedicated registers to usb host only operation. each set consists of two identical registers (unless otherwise noted); one for host port 1 and on e for host port 2. these register sets are covered in this section and summarized in figure 8-15 . 8.4.1 host n control register [r/w] ? host 1 control register 0xc080 ? host 2 control register 0xc0a0 figure 8-16. host n control register register description the host n control register allows high-level usb transaction control. preamble enable (bit 7) the preamble enable bit enables or disables the transmission of a preamble packet before all low-speed packets. this bit should only be set when communicating with a low-speed device. 1: enable preamble packet 0: disable preamble packet sequence select (bit 6) the sequence select bit sets the data toggle for the next pack et. this bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: send data1 0: send data0 figure 8-15. usb host only register register name address (host 1/host 2) r/w host n control register 0xc080/0xc0a0 r/w host n address register 0xc082/0xc0a2 r/w host n count register 0xc084/0xc0a4 r/w host n endpoint status register 0xc086/0xc0a6 r host n pid register 0xc086/0xc0a6 w host n count result r egister 0xc088/0xc0a8 r host n device address register 0xc088/0xc0a8 w host n interrupt enable register 0xc08c/0xc0ac r/w host n status register 0xc090/0xc0b0 r/w host n sof/eop count register 0xc092/0xc0b2 r/w host n sof/eop counter register 0xc094/0xc0b4 r host n frame register 0xc096/0xc0b6 r bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field preamble enable sequence select sync enable iso enable reserved arm enable read/write r/w r/w r/w r/w - - - r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 21 of 82 sync enable (bit 5) the sync enable bit synchronizes the transfer with the sof pack et in full-speed mode and the eop packet in low-speed mode. 1: the next enabled packet will be transferred after the sof or eop packet is transmitted 0: the next enabled packet will be transferred as soon as the sie is free iso enable (bit 4) the iso enable bit enables or disables an isochronous transaction. 1: enable isochronous transaction 0: disable isochronous transaction arm enable (bit 0) the arm enable bit arms an endpoint and starts a transaction. this bit is automatically cleared to ?0? when a transaction is complete. 1: arm endpoint and begin transaction 0: endpoint disarmed reserved all reserved bits must be written as ?0?. 8.4.2 host n address register [r/w] ? host 1 address register 0xc082 ? host 2 address register 0xc0a2 figure 8-17. host n address register register description the host n address register is used as the base pointe r into memory space for the current host transactions. address (bits [15:0]) the address field sets the address pointer into internal ram or rom. 8.4.3 host n count register [r/w] ? host 1 count register 0xc084 ? host 2 count register 0xc0a4 figure 8-18. host n count register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 22 of 82 register description the host n count register is used to hold the number of bytes (packet length) for the current transaction. the maximum packet length is 1023 bytes in iso mode. the host count value is us ed to determine how many bytes to transmit, or the maximum number of bytes to receive. if the number of received bytes is greater then the host count value then an overflow condition wil l be flagged by the overflow bit in the host n endpoint status register. count (bits [9:0]) the count field sets the value for the current transaction data packet length. this value is retained when switching between ho st and device mode, and back again. reserved all reserved bits must be written as ?0?. 8.4.4 host n endpoint status register [r] ? host 1 endpoint status register 0xc086 ? host 2 endpoint status register 0xc0a6 figure 8-19. host n endpoint status register register description the host n endpoint status regist er is a read only register that provides status for the last usb transaction. overflow flag (bit 11) the overflow flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the host n count register. the overflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the host n count register. the underflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur stall flag (bit 7) the stall flag bit indicates that the peripheral device replied with a stall in the last transaction. 1: device returned stall 0: device did not return stall nak flag (bit 6) the nak flag bit indicates that the peripheral device replied with a nak in the last transaction. 1: device returned nak 0: device did not return nak length exception flag (bit 5) the length exception flag bit indicates the received data in the data stage of the last transaction does not equal the maximum host count specified in the host n count register. a length exception can either mean an overflow or underflow and the overflow and underflow flags (bits 11 and 10, respec- tively) should be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag reserved read/write - - - - r r - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag read/write r r r - r r r r default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 23 of 82 sequence status (bit 3) the sequence status bit indicates the state of the last received data toggle from the device. firmware is responsible for monit oring and handling the sequence status. the sequence bit is only valid if the ack bit is set to ?1?. the sequence bit is set to ?0? w hen an error is detected in the transaction and the error bit will be set. 1: data1 0: data0 timeout flag (bit 2) the timeout flag bit indicates if a timeout condition occurred fo r the last transaction. a timeout condition can occur when a d evice either takes too long to respond to a usb host request or takes too long to respond with a handshake. 1: timeout occurred 0: timeout did not occur error flag (bit 1) the error flag bit indicates a transaction failed for any reason other than the following: timeout , receiving a nak, or receivi ng a stall. overflow and underflow are not cons idered errors and do not affect this bit. crc5 and crc16 errors will result in an error flag along with receiving incorrect packet types. 1: error detected 0: no error detected ack flag (bit 0) the ack flag bit indicates two different conditions depending on the transfer type. for non-isochronous transfers, this bit represents a transaction ending by receiving or sending an ack packet. for isochronous transfers, this bit represents a successful transaction that will not be represented by an ack packet. 1: for non-isochronous transfers, the transaction was acked. for isochronous transfers, the transaction was completed successfully. 0: for non-isochronous transfers, the tran saction was not acked. for isochronous trans fers, the transaction did not completed successfully. 8.4.5 host n pid register [w] ? host 1 pid register 0xc086 ? host 2 pid register 0xc0a6 figure 8-20. host n pid register register description the host n pid register is a wr ite-only register that provides the pid and endpoint information to the usb sie to be used in th e next transaction. pid select (bits [7:4]) the pid select field defined as in table 8-7 . ack and nak tokens are automatically sent based on settings in the host n control register and do not need to be written in this register. bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field pid select endpoint select read/write w w w w w w w w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 24 of 82 endpoint select (bits [3:0]) the endpoint field which allows addressing up to 16 different endpoints. reserved all reserved bits must be written as ?0?. 8.4.6 host n count result register [r] ? host 1 count result register 0xc088 ? host 2 count result register 0xc0a8 figure 8-21. host n count result register register description the host n count result register is a read only register that co ntains the size difference in bytes between the host count valu e specified in the host n count register a nd the last packet received. if an overflow or underflow conditio n occurs, i.e., the re ceived packet length differs from the value specified in the host n c ount register, the length exception flag bit in the host n endpoi nt status register will be set. the value in this register is only valid when the length exception flag bit is set and the error f lag bit is not set; both bits are in the host n endpoint status register. result (bits [15:0]) the result field contains the differences in bytes between the received packet and the value specified in the host n count regi ster. if an overflow condition occurs, result [15:10] is set to ?111111?, a 2?s complement value indicating the additional byte count of the received packet. if an underflow condition occurs, result [1 5:0] indicates the excess bytes count (number of bytes not used ). reserved all reserved bits must be written as ?0?. table 8-7. pid select definition pid type pid select [7:4] set-up 1101 (d hex) in 1001 (9 hex) out 0001 (1 hex) sof 0101 (5 hex) preamble 1100 (c hex) nak 1010 (a hex) stall 1110 (e hex) data0 0011 (3 hex) data1 1011 (b hex) bit # 15 14 13 12 11 10 9 8 field result... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...result read/write r r r r r r r r default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 25 of 82 8.4.7 host n device address register [w] ? host 1 device address register 0xc088 ? host 2 device address register 0xc0a8 figure 8-22. host n device address register register description the host n device address register is a write-only register that contains the usb device address that the host wishes to communicate with. address (bits [6:0]) the address field contains the value of the usb address for the next device that the host is going to communicate with. this value needs to be written by firmware. reserved all reserved bits must be written as ?0?. 8.4.8 host n interrupt enable register [r/w] ? host 1 interrupt enable register 0xc08c ? host 2 interrupt enable register 0xc0ac figure 8-23. host n interrupt enable register register description the host n interrupt enable register will allow control over host-related interrupts. in this register a bit set to ?1? enables the corresponding interrupt while ?0? disables the interrupt. vbus interrupt enable (bit 15) the vbus interrupt enable bit enables or disables the otg vbus interrupt. when enabled this interrupt triggers on both rising and falling edge of vbus at the 4.4v status (only supported in po rt 1a). this bit is only available for host 1 and is a reserve d bit in host 2. 1: enable vbus interrupt 0: disable vbus interrupt bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved read/write r/w r/w - - - - r/w - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved port a wake interrupt enable reserved port a connect change interrupt enable reserved done interrupt enable read/write - r/w - r/w - - - r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 26 of 82 id interrupt enable (bit 14) the id interrupt enable bit enables or disables the otg id interrupt. when enabled this interrupt triggers on both rising and f alling edge of otg id pin (only supported in port 1a). this bit is only available for host 1 and is a reserved bit in host 2. 1: enable id interrupt 0: disable id interrupt sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit enables or disables the sof/eop timer interrupt. 1: enable sof/eop timer interrupt 0: disable sof/eop timer interrupt port a wake interrupt enable (bit 6) the port a wake interrupt enable bit enables or disables the remote wakeup interrupt for port a. 1: enable remote wakeup interrupt for port a 0: disable remote wakeup interrupt for port a port a connect change interrupt enable (bit 4) the port a connect change interrupt enable bit enables or disa bles the connect change interrupt on port a. this interrupt triggers when either a device is inserted (se0 state to j state) or a device is removed (j state to se0 state). 1: enable connect change interrupt 0: disable connect change interrupt done interrupt enable (bit 0) the done interrupt enable bit enables or disables the usb transfer done interrupt. the usb transfer done triggers when either the host responding with and ack, or a device responds with any of the following: ack, nak, stal l, or timeout. this interrupt is used for both port a and port b. 1: enable usb transfer done interrupt 0: disable usb transfer done interrupt reserved all reserved bits must be written as ?0?. 8.4.9 host n status register [r/w] ? host 1 status register 0xc090 ? host 2 status register 0xc0b0 figure 8-24. host n status register register description the host n status register provides status information for hos t operation. pending interrupts can be cleared by writing a ?1? t o the corresponding bit. this register can be accessed by the hpi interface. bit # 15 14 13 12 11 10 9 8 field vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved read/write r/w r/w - - - - r/w - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field reserved port a wake interrupt flag reserved port a connect change interrupt flag reserved port a se0 status reserved done interrupt flag read/write - r/w - r/w - r/w - r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 27 of 82 vbus interrupt flag (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt trig gers on both the rising and falling edge of vbus at 4.4v. this bit is only available for host 1 and is a reserved bit in host 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id in terrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of the otg id pin. this bit is only available for host 1 and is a reserved bit in host 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bit indicates the status of the sof/ eop timer interrupt. this bit triggers ?1? when the sof/eop time r expires. 1: interrupt triggered 0: interrupt did not trigger port a wake interrupt flag (bit 6) the port a wake interrupt flag bit indicates remote wakeup on porta 1: interrupt triggered 0: interrupt did not trigger port a connect change interrupt flag (bit 4) the port a connect change interrupt flag bit indicates the status of the connect change interrupt on port a. this bit triggers ?1? on either a rising edge or falling edge of a usb reset condition ( device inserted or removed). toge ther with the port a se0 sta tus bit, it can be determined whether a device was inserted or removed. 1: interrupt triggered 0: interrupt did not trigger port a se0 status (bit 2) the port a se0 status bit indicates if port a is in an se0 stat e or not. together with the port a connect change interrupt flag bit, it can be determined whether a device was inse rted (non-se0 condition) or removed (se0 condition). 1: se0 condition 0: non-se0 condition done interrupt flag (bit 0) the done interrupt flag bit indicates the status of the usb transfer done interrupt. the usb transfer done triggers when either the host responding with and ack, or a device responds with any of the following: ack, nak, stal l, or timeout. this interrupt is used for both port a and port b. 1: interrupt triggered 0: interrupt did not trigger
CY7C67200 document #: 38-08014 rev. *f page 28 of 82 8.4.10 host n sof/eop count register [r/w] ? host 1 sof/eop count register 0xc092 ? host 2 sof/eop count register 0xc0b2 figure 8-25. host n sof/eop count register register description the host n sof/eop count register contai ns the sof/eop count value that is loaded into the sof/eop counter. this value is loaded each time the sof/eop counter counts down to zero. the default value set in this register at power-up is 0x2ee0, which will generate a 1-ms time frame. the sof/eop counter is a do wn counter decremented at a 12-mh z rate. when this register is read, the value returned is the programmed sof/eop count value. count (bits [13:0]) the count field sets the sof/eop counter duration. reserved all reserved bits must be written as ?0?. 8.4.11 host n sof/eop counter register [r] ? host 1 sof/eop counter register 0xc094 ? host 2 sof/eop counter register 0xc0b4 figure 8-26. host n sof/eop counter register register description the host n sof/eop counter register contains the current va lue of the sof/eop down counter. this value can be used to determine the time remaining in the current frame. counter (bits [13:0]) the counter field contains the current value of the sof/eop down counter. bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r/w r/w r/w r/w r/w r/w default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...counter read/write r r r r r r r r default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 29 of 82 8.4.12 host n frame register [r] ? host 1 frame register 0xc096 ? host 2 frame register 0xc0b6 figure 8-27. host n frame register register description the host n frame register maintains the nex t frame number to be transmitted (current frame number + 1). this value is updated after each sof transmission. this register resets to 0x0000 after each cpu write to the host n sof/eop count register (host 1: 0xc092, host 2: 0xc0b2). frame (bits [10:0]) the frame field contains the next frame number to be transmitted. reserved all reserved bits must be written as ?0?. 8.5 usb device only registers there are ten sets of usb device only regi sters. all sets consist of at least two re gisters, one for device port 1 and one for device port 2. in addition, each device port has eight possible endpoin ts. this gives each endpoint register set eight registers for e ach device port for a total of 16 registers per set. the usb devi ce only registers are covered in this section and summarized in figure 8-28 . 8.5.1 device n endpoint n control register [r/w] ? device n endpoint 0 control register [device 1: 0x0200 device 2: 0x0280] ? device n endpoint 1 control register [device 1: 0x0210 device 2: 0x0290] ? device n endpoint 2 control register [device 1: 0x0220 device 2: 0x02a0] ? device n endpoint 3 control register [device 1: 0x0230 device 2: 0x02b0] ? device n endpoint 4 control register [device 1: 0x0240 device 2: 0x02c0] ? device n endpoint 5 control register [device 1: 0x0250 device 2: 0x02d0] ? device n endpoint 6 control register [device 1: 0x0260 device 2: 0x02e0] ? device n endpoint 7 control register [device 1: 0x0270 device 2: 0x02f0] bit # 15 14 13 12 11 10 9 8 field reserved frame... read/write - - - - - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 figure 8-28. usb device only registers register name address (device 1/device 2) r/w device n endpoint n control register 0x02n0 r/w device n endpoint n address register 0x02n2 r/w device n endpoint n count register 0x02n4 r/w device n endpoint n status register 0x02n6 r/w device n endpoint n count result register 0x02n8 r/w device n interrupt enable register 0xc08c/0xc0ac r/w device n address register 0xc08e/0xc0ae r/w device n status regi ster 0xc090/0xcb0 r/w device n frame number register 0xc092/0xc0b2 r device n sof/eop count register 0xc094/0xc0b4 w
CY7C67200 document #: 38-08014 rev. *f page 30 of 82 figure 8-29. device n endpoint n control register register description the device n endpoint n control register provides control over a single ep in device mode. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n control register. in/out ignore enable (bit 6) the in/out ignore enable bit forces endpoint 0 (ep0) to ignore all in and out requests. this bit must be set so that ep0 only excepts set-up packets at the start of each transfer. this bit must be cleared to except in/out transactions. this bit only applies to ep0. 1: ignore in/out requests 0: do not ignore in/out requests sequence select (bit 6) the sequence select bit determines whether a data0 or a data1 will be sent for the next data toggle. this bit has no effect on receiving data packets, sequence checking must be handled in firmware. 1: send a data1 0: send a data0 stall enable (bit 5) the stall enable bit sends a stall in response to the next request (unless it is a set-up request, which are always acked). this is a sticky bit and continues to respond with stalls until cleared by firmware. 1: send stall 0: do not send stall iso enable (bit 4) the iso enable bit enables and disables an isochronous transaction. this bit is only valid for eps 1?7 and has no function for ep0. 1: enable isochronous transaction 0: disable isochronous transaction nak interrupt enable (bit 3) the nak interrupt enable bit enables and disables the gener- ation of an endpoint n interrupt when the device responds to the host with a nak. the endpoint n interrupt enable bit in the device n interrupt enable register must also be set. when a nak is sent to the host, the corresponding ep interrupt flag in the device n status register will be set. in addition, the nak flag in the device n endpoint n status register will be set. 1: enable nak interrupt 0: disable nak interrupt direction select (bit 2) the direction select bit needs to be set according to the expected direction of the next data stage in the next trans- action. if the data stage directio n is different from what is set in this bit, it will get naked and either the in exception flag or the out exception flag will be set in the device n endpoint n status register. if a set-up packe t is received and the direction select bit is set incorrectly, the set-up will get acked and the set-up status flag will be set (refer to the set-up bit of the device n endpoint n status register for details). 1: out transfer (host to device) 0: in transfer (device to host) enable (bit 1) the enable bit must be set to allow transfers to the endpoint. if enable is set to ?0? then all usb traffic to this endpoint is ignored. if enable is set ?1? and arm enable (bit 0) is set ?0? then naks will automatically be returned from this endpoint (except set-up packets which are always acked as long as the enable bit is set.) 1: enable transfers to an endpoint 0: do not allow transfers to an endpoint arm enable (bit 0) the arm enable bit arms the endpoint to transfer or receive a packet. this bit is cleared to ?0? when a transaction is complete. 1: arm endpoint 0: endpoint disarmed reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 31 of 82 8.5.2 device n endpoint n address register [r/w] ? device n endpoint 0 address register [device 1: 0x0202 device 2: 0x0282] ? device n endpoint 1 address register [device 1: 0x0212 device 2: 0x0292] ? device n endpoint 2 address register [device 1: 0x0222 device 2: 0x02a2] ? device n endpoint 3 address register [device 1: 0x0232 device 2: 0x02b2] ? device n endpoint 4 address register [device 1: 0x0242 device 2: 0x02c2] ? device n endpoint 5 address register [device 1: 0x0252 device 2: 0x02d2] ? device n endpoint 6 address register [device 1: 0x0262 device 2: 0x02e2] ? device n endpoint 7 address register [device 1: 0x0272 device 2: 0x02f2] figure 8-30. device n endpoint n address register register description the device n endpoint n address register is used as the base pointer into memory space for the current endpoint transaction. there are a total of eight endpoints for each of the two ports. al l endpoints have the same definition for their device n endpo int n address register. address (bits [15:0]) the address field sets the base address for t he current transaction on a signal endpoint. 8.5.3 device n endpoint n count register [r/w] ? device n endpoint 0 count register [device 1: 0x0204 device 2: 0x0284] ? device n endpoint 1 count register [device 1: 0x0214 device 2: 0x0294] ? device n endpoint 2 count register [device 1: 0x0224 device 2: 0x02a4] ? device n endpoint 3 count register [device 1: 0x0234 device 2: 0x02b4] ? device n endpoint 4 count register [device 1: 0x0244 device 2: 0x02c4] ? device n endpoint 5 count register [device 1: 0x0254 device 2: 0x02d4] ? device n endpoint 6 count register [device 1: 0x0264 device 2: 0x02e4] ? device n endpoint 7 count register [device 1: 0x0274 device 2: 0x02f4] figure 8-31. device n endpoint n count register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 32 of 82 register description the device n endpoint n count register designates the maximum pa cket size that can be received fr om the host for out transfers for a single endpoint. this register also designates the packet size to be sent to the host in response to the next in token fo r a single endpoint. the maximum packet length is 1023 bytes in iso mode. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition fo r their device n endpoint n count register. count (bits [9:0]) the count field sets the current transaction packet length for a single endpoint. reserved all reserved bits must be written as ?0?. 8.5.4 device n endpoint n status register [r/w] ? device n endpoint 0 status register [device 1: 0x0206 device 2: 0x0286] ? device n endpoint 1 status register [device 1: 0x0216 device 2: 0x0296] ? device n endpoint 2 status register [device 1: 0x0226 device 2: 0x02a6] ? device n endpoint 3 status register [device 1: 0x0236 device 2: 0x02b6] ? device n endpoint 4 status register [device 1: 0x0246 device 2: 0x02c6] ? device n endpoint 5 status register [device 1: 0x0256 device 2: 0x02d6] ? device n endpoint 6 status register [device 1: 0x0266 device 2: 0x02e6] ? device n endpoint 7 status register [device 1: 0x0276 device 2: 0x02f6] figure 8-32. device n endpoint n status register register description the device n endpoint n status register provides packet status information for the last transaction received or transmitted. this register is updated in hardware and does not need to be cleared by firmware. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n status register. the device n endpoint n status register is a memory-based register that must be initialized to 0x0000 before usb device operations are initiated. after in itialization, this register must not be written to again. overflow flag (bit 11) the overflow flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the device n endpoint n count register. the overflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the device n endpoint n count register. the underflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur out exception flag (bit 9) the out exception flag bit indicates when the device received an out packet when armed for an in. 1: received out when armed for in 0: received in when armed for in i n exception flag (bit 8) the in exception flag bit indicates when the device received an in packet when armed for an out. 1: received in when armed for out 0: received out when armed for out stall flag (bit 7) bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag out exception flag in exception flag read/write - - - - r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag set-up flag sequence flag time-out flag error flag ack flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 33 of 82 the stall flag bit indicates that a stall packet was sent to the host. 1: stall packet was sent to the host 0: stall packet was not sent nak flag (bit 6) the nak flag bit indicates that a nak packet was sent to the host. 1: nak packet was sent to the host 0: nak packet was not sent length exception flag (bit 5) the length exception flag bit indicates the received data in the data stage of the last transaction does not equal the maximum endpoint count specified in the device n endpoint n count register. a length exception can either mean an overflow or underflow and the overflow and underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur set-up flag (bit 4) the set-up flag bit indicates that a set-up packet was received. in device mode set-up packets get stored at memory location 0x0300 for device 1 and 0x0308 for device 2. set-up packets are always accepted regardless of the direction select and arm enable bit settings as long as the device n ep n control register enable bit is set. 1: set-up packet was received 0: set-up packet was not received sequence flag (bit 3) the sequence flag bit indicates whether the last data toggle received was a data1 or a data0. this bit has no effect on receiving data packets, sequence checking must be handled in firmware. 1: data1 was received 0: data0 was received time-out flag (bit 2) the time-out flag bit indicates whether a time-out condition occurred on the last transacti on. on the device side, a time- out can occur if the device sends a data packet in response to an in request but then does not receive a handshake packet in a predetermined time. it can also occur if the device does not receive the data stage of an out transfer in time. 1: time-out occurred 0: time-out condition did not occur error flag (bit 2) the error flag bit is set if a crc5 and crc16 error occurs, or if an incorrect packet type is received. overflow and underflow are not considered errors and do not affect this bit. 1: error occurred 0: error did not occur ack flag (bit 0) the ack flag bit indicates whether the last transaction was acked. 1: ack occurred 0: ack did not occur
CY7C67200 document #: 38-08014 rev. *f page 34 of 82 8.5.5 device n endpoint n count result register [r/w] ? device n endpoint 0 count result register [device 1: 0x0208 device 2: 0x0288] ? device n endpoint 1 count result register [device 1: 0x0218 device 2: 0x0298] ? device n endpoint 2 count result register [device 1: 0x0228 device 2: 0x02a8] ? device n endpoint 3 count result register [device 1: 0x0238 device 2: 0x02b8] ? device n endpoint 4 count result register [device 1: 0x0248 device 2: 0x02c8] ? device n endpoint 5 count result register [device 1: 0x0258 device 2: 0x02d8] ? device n endpoint 6 count result register [device 1: 0x0268 device 2: 0x02e8] ? device n endpoint 7 count result register [device 1: 0x0278 device 2: 0x02f8] figure 8-33. device n endpoint n count result register register description the device n endpoint n count result register contains the size difference in bytes between the endpoint count specified in the device n endpoint n count register and the last packet received. if an overflow or underflow co ndition occurs. i.e. the receive d packet length differs from the value specified in the device n endpoint n count register, the length exception flag bit in the device n endpoint n status register will be set. the value in this register is only value wh en the length exception flag bit is set and the error flag bit is not set, both bits are in the device n endpoint n status register. the device n endpoint n count result regist er is a memory based register that must be initialized to 0x0000 before usb device operations are initiated. after initialization, this register must no t be written to again. result (bits [15:0]) the result field contains the differences in bytes between the re ceived packet and the value specified in the device n endpoint n count register. if an overflow condition occurs, result [15:10] is set to ?111111?, a 2?s complement value indicating the add itional byte count of the received packet. if an underflow condition occu rs, result [15:0] indicates the excess bytes count (number of bytes not used). reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field result... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...result read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 35 of 82 8.5.6 device n interrupt enable register [r/w] ? device 1 interrupt enable register 0xc08c ? device 2 interrupt enable register 0xc0ac figure 8-34. device n interrupt enable register register description the device n interrupt enable re gister provides control over device related interrupts including eight different endpoint interrupts. vbus interrupt enable (bit 15) the vbus interrupt enable bit enables or disables the otg vbus interrupt. when enabled this interrupt triggers on both rising and falling edge of vbus at the 4.4v status (only supported in port 1a). this bit is only available for device 1 and is a reserved bit in device 2. 1: enable vbus interrupt 0: disable vbus interrupt id interrupt enable (bit 14) the id interrupt enable bit enables or disables the otg id interrupt. when enabled this interrupt triggers on both rising and falling edge of otg id pin (only supported in port 1a). this bit is only available for device 1 and is a reserved bit in device 2. 1: enable id interrupt 0: disable id interrupt sof/eop time-out interrupt enable (bit 11) the sof/eop time-out inte rrupt enable bit enables or disables the sof/eop time-out interrupt. when enabled this interrupt triggers when the usb host fails to send a sof or eop packet within the time period specified in the device n sof/eop count register. in addition, the device n frame register counts the number of times the sof/eop timeout interrupt triggers between receiving sof/eops. 1: sof/eop time-out occurred 0: sof/eop time-out did not occur sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit enables or disables the sof/eop received interrupt. 1: enable sof/eop received interrupt 0: disable sof/eop received interrupt reset interrupt enable (bit 8) the reset interrupt enable bit enables or disables the usb reset detected interrupt 1: enable usb reset detected interrupt 0: disable usb reset detected interrupt ep7 interrupt enable (bit 7) the ep7 interrupt enable bit enables or disables endpoint seven (ep7) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak re sponses triggers this interrupt. 1: enable ep7 transaction done interrupt 0: disable ep7 transaction done interrupt ep6 interrupt enable (bit 6) the ep6 interrupt enable bit enables or disables endpoint seven (ep6) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak re sponses triggers this interrupt. 1: enable ep6 transaction done interrupt 0: disable ep6 transaction done interrupt bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop time-out interrupt enable reserved sof/eop interrupt enable reset interrupt enable read/write r/w r/w - - r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 36 of 82 ep5 interrupt enable (bit 5) the ep5 interrupt enable bit enables or disables endpoint seven (ep5) transaction done in terrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so th at nak responses triggers this interrupt. 1: enable ep5 transaction done interrupt 0: disable ep5 transaction done interrupt ep4 interrupt enable (bit 4) the ep4 interrupt enable bit enables or disables endpoint seven (ep4) transaction done in terrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so th at nak responses triggers this interrupt. 1: enable ep4 transaction done interrupt 0: disable ep4 transaction done interrupt ep3 interrupt enable (bit 3) the ep3 interrupt enable bit enables or disables endpoint seven (ep3) transaction done in terrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so th at nak responses triggers this interrupt. 1: enable ep3 transaction done interrupt 0: disable ep3 transaction done interrupt ep2 interrupt enable (bit 2) the ep2 interrupt enable bit enables or disables endpoint seven (ep2) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak re sponses triggers this interrupt. 1: enable ep2 transaction done interrupt 0: disable ep2 transaction done interrupt ep1 interrupt enable (bit 1) the ep1 interrupt enable bit enables or disables endpoint seven (ep1) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak re sponses triggers this interrupt. 1: enable ep1 transaction done interrupt 0: disable ep1 transaction done interrupt ep0 interrupt enable (bit 0) the ep0 interrupt enable bit enables or disables endpoint seven (ep0) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s given endpoint: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak re sponses triggers this interrupt. 1: enable ep0 transaction done interrupt 0: disable ep0 transaction done interrupt reserved all reserved bits must be written as ?0?.
CY7C67200 document #: 38-08014 rev. *f page 37 of 82 8.5.7 device n address register [w] ? device 1 address register 0xc08e ? device 2 address register 0xc0ae figure 8-35. device n address register register description the device n address register holds the device address assigned by the host. this register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address. only usb data sent to the address contained in this register will be responded to, all others are ignored. address (bits [6:0]) the address field contains the usb address of the device assigned by the host. reserved all reserved bits must be written as ?0?. 8.5.8 device n status register [r/w] ? device 1 status register 0xc090 ? device 2 status register 0xc0b0 figure 8-36. device n status register register description the device n status register provides status information for device operation. pending interrupts can be cleared by writing a ?1? to the corresponding bit. this register can be accessed by the hpi interface. vbus interrupt flag (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of vbus at 4.4v. this bit is only available for device 1 and is a reserved bit in device 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of the otg id pin. this bit is only available for device 1 and is a reserved bit in device 2. 1: interrupt triggered 0: interrupt did not trigger bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag read/write r/w r/w - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 38 of 82 sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bi t indicates if the sof/eop received interrupt has triggered. 1: interrupt triggered 0: interrupt did not trigger reset interrupt flag (bit 8) the reset interrupt flag bit indicates if the usb reset detected interrupt has triggered. 1: interrupt triggered 0: interrupt did not trigger ep7 interrupt flag (bit 7) the ep7 interrupt flag bit indicates if the endpoint seven (ep7) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep6 interrupt flag (bit 6) the ep6 interrupt flag bit indicates if the endpoint six (ep6) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out occurs, in exception error, or out except ion error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep5 interrupt flag (bit 5) the ep5 interrupt flag bit indicates if the endpoint five (ep5) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out occurs, in exception error, or out except ion error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep4 interrupt flag (bit 4) the ep4 interrupt flag bit indicates if the endpoint four (ep4) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out occurs, in exception error, or out except ion error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep3 interrupt flag (bit 3) the ep3 interrupt flag bit indicates if the endpoint three (ep3) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep2 interrupt flag (bit 2) the ep2 interrupt flag bit indicates if the endpoint two (ep2) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep1 interrupt flag (bit 1) the ep1 interrupt flag bit indicates if the endpoint one (ep1) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep0 interrupt flag (bit 0) the ep0 interrupt flag bit indicates if the endpoint zero (ep0) transaction done interrupt has triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stal l, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger reserved all reserved bits must be written as ?0?.
CY7C67200 document #: 38-08014 rev. *f page 39 of 82 8.5.9 device n frame number register [r] ? device 1 frame number register 0xc092 ? device 2 frame number register 0xc0b2 figure 8-37. device n frame number register register description the device n frame number register is a read only register t hat contains the frame number of the last sof packet received. this register also contains a c ount of sof/eop timeout occurrences. sof/eop time-out flag (bit 15) the sof/eop time-out flag bit indicates when an sof/eop timeout interrupt occurs. 1: an sof/eop time-out interrupt occurred 0: an sof/eop time-out interrupt did not occur sof/eop time-out interrupt counter (bits [14:12]) the sof/eop time-out interrupt counter field increments by 1 from 0 to 7 for each so f/eop time-out interru pt. this field resets to 0 when a sof/eop is received. this fiel d is only updated when the sof/eop time-out interrupt enable bit in the device n interrupt enable register is set. frame (bits [10:0]) the frame field contains the frame number from the last received sof packet in full speed mode. this field has no function for low speed mode. if a sof timeout occurs, this field contains the last received frame number. 8.5.10 device n sof/eop count register [w] ? device 1 sof/eop count register 0xc094 ? device 2 sof/eop count register 0xc0b4 figure 8-38. device n sof/eop count register register description the device n sof/eop count register must be written with the time expected betw een receiving a sof/eops. if the sof/eop counter expires before an sof/eop is received, an sof/eo p time-out interrupt can be generated. the sof/eop time-out interrupt enable and sof/eop time-out interrupt flag are located in the device n interrupt enable and status registers, respec- tively. bit # 15 14 13 12 11 10 9 8 field sof/eop time-out flag sof/eop time-out interrupt counter reserved frame... read/write r r r r - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r r r r r r default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r r r r r r r r default 1 1 1 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 40 of 82 the sof/eop count must be set slightly greater t han the expected sof/eop interval. the sof/eop counter decrements at a 12-mhz rate. therefore in the case of an expected 1-ms sof/eo p interval, the sof/eop count must be set slightly greater then 0x2ee0. count (bits [13:0]) the count field contains the current value of the sof/eop down counter. at power-up and reset, this value is set to 0x2ee0 and for expected 1-ms sof/eop intervals, this sof/eop count should be increased slightly. reserved all reserved bits must be written as ?0?. 8.6 otg control registers there is one register dedicated for otg operation. this register is covere d in this section and summarized in figure 8-39 . 8.6.1 otg control register [0xc098] [r/w] figure 8-40. otg control register register description the otg control register allows control and monitoring over the otg port on port1a. vbus pull-up enable (bit 13) the vbus pull-up enable bit enables or disables a 500 ohm pull up resistor onto otg vbus. 1: 500 ohm pull up resistor enabled 0: 500 ohm pull up resistor disabled receive disable (bit 12) the receive disable bit enables or powers down (disables) the otg receiver section. 1: otg receiver powered down and disabled 0: otg receiver enabled figure 8-39. otg registers register name address r/w otg control register c098h r/w bit # 15 14 13 12 11 10 9 8 field reserved vbus pull-up enable receive disable charge pump enable vbus discharge enable d+ pull-up enable d? pull-up enable read/write - - r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field d+ pull-down enable d? pull-down enable reserved otg data status id status vbus valid flag read/write r/w r/w - - - r r r default 0 0 0 0 0 x x x
CY7C67200 document #: 38-08014 rev. *f page 41 of 82 charge pump enable (bit 11) the charge pump enable bit enables or disables the otg vbus charge pump. 1: otg vbus charge pump enabled 0: otg vbus charge pump disabled vbus discharge enable (bit 10) the vbus discharge enable bit enables or disables a 2k ohm discharge pull down resistor onto otg vbus. 1: 2k ohm pull down resistor enabled 0: 2k ohm pull down resistor disabled d+ pull-up enable (bit 9) the d+ pull-up enable bit enables or disables a pull up resistor on the otg d+ data line. 1: otg d+ dataline pull up resistor enabled 0: otg d+ dataline pull up resistor disabled d? pull-up enable (bit 8) the d? pull-up enable bit enables or disables a pull up resistor on the otg d? data line. 1: otg d? dataline pull up resistor enabled 0: otg d? dataline pull up resistor disabled d+ pull-down enable (bit 7) the d+ pull-down enable bit enables or disables a pull down resistor on the otg d+ data line. 1: otg d+ dataline pull down resistor enabled 0: otg d+ dataline pull down resistor disabled d? pull-down enable (bit 6) the d? pull-down enable bit enables or disables a pull down resistor on the otg d- data line. 1: otg d? dataline pull down resistor enabled 0: otg d? dataline pull down resistor disabled otg data status (bit 2) the otg data status bit is a read only bit and indicates the ttl logic state of the otg vbus pin. 1: otg vbus is greater than 2.4v 0: otg vbus is less than 0.8v id status (bit 1) the id status bit is a read only bit that indicates the state of the otg id pin on port a. 1: otg id pin is not connected directly to ground (>10k ohm) 0: otg id pin is connected directly ground (< 10 ohm) vbus valid flag (bit 0) the vbus valid flag bit indicates whether otg vbus is greater than 4.4v. after turning on vbus, firmware should wait at least 10 s before this reading this bit. 1: otg vbus is greater then 4.4v 0: otg vbus is less then 4.4v reserved all reserved bits must be written as ?0?. 8.7 gpio registers there are seven registers dedicated for gpio operations. these seven registers are covered in this section and summa- rized in figure 8-41 . figure 8-41. gpio registers register name address r/w gpio control register 0xc006 r/w gpio0 output data register 0xc01e r/w gpio0 input data register 0xc020 r gpio0 direction register 0xc022 r/w gpio1 output data register 0xc024 r/w gpio1 input data register 0xc026 r gpio1 direction register 0xc028 r/w
CY7C67200 document #: 38-08014 rev. *f page 42 of 82 8.7.1 gpio control register [0xc006] [r/w] figure 8-42. gpio control register register description the gpio control register co nfigures the gpio pins for various interface options. it also controls the polarity of the gpio interrupt on irq0 (gpio24). write protect enable (bit 15) the write protect enable bit enables or disables the gpio write protect. when write prot ect is enabled, the gpio mode select [15:8] bits are read only until a chip reset. 1: enable write protect 0: disable write protect sas enable (bit 11) the sas enable bit, when in spi mode, reroutes the spi port spi_nssi pin to gpio[15] rather then gpio[9]. 1: reroute spi_nss to gpio[15] 0: leave spi_nss on gpio[9] mode select (bits [10:8]) the mode select field selects how gpio[15:0] and gpio[24:19] are used as defined in table 8-8 . hss enable (bit 7) the hss enable bit routes hss to gpio[15:12]. 1: hss is routed to gpio 0: hss is not routed to gpio?s. gpio[15:12] are free for other purposes. spi enable (bit 5) the spi enable bit routes spi to gpio[11:8]. if the sas enable bit is set, it overrides and routes the spi_nssi pin to gpio15. 1: spi is routed to gpio[11:8] 0: spi is not routed to gpio[1 1:8]. gpio[11:8] are free for other purposes. interrupt 0 polarity select (bit 1) the interrupt 0 polarity select bit selects the polarity for irq0. 1: sets irq0 to rising edge 0: sets irq0 to falling edge interrupt 0 enable (bit 0) the interrupt 0 enable bit enables or disables irq0. the gpio bit on the interrupt enable register must also be set in order for this for this interrupt to be enabled. 1: enable irq0 0: disable irq0 reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field write protect enable reserved reserved sas enable mode select read/write r/w - r - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss enable reserved spi enable reserved interrupt 0 polarity select interrupt 0 enable read/write r/w - r/w - - - r/w r/w default 0 0 0 0 0 0 0 0 table 8-8. mode select definition mode select [10:8] gpio configuration 111 reserved 110 scan ? (hw) scan diagnostic. for pro- duction test only. not for normal operation 101 hpi ? host port interface 100 reserved 011 reserved 010 reserved 001 reserved 000 gpio ? general purpose input output
CY7C67200 document #: 38-08014 rev. *f page 43 of 82 8.7.2 gpio 0 output data register [0xc01e] [r/w] figure 8-43. gpio 0 output data register register description the gpio 0 output data register controls th e output data of the gpio pins. the gpio 0 output data register controls gpio15 to gpio0 while the gpio 1 output data register controls gpio 31 to gpio19. when read, this register reads back the last data written, not the data on pins configur ed as inputs (see input data register). writing a 1 to any bit will output a high voltage on the corresponding gpio pin. reserved all reserved bits must be written as ?0?. 8.7.3 gpio 1 output data register [0xc024] [r/w] figure 8-44. gpio n output data register register description the gpio 1 output data register controls th e output data of the gpio pins. the gpio 0 output data register controls gpio15 to gpio0 while the gpio 1 output data register controls gpio 31 to gpio19. when read, this register reads back the last data written, not the data on pins configur ed as inputs (see input data register). writing a 1 to any bit will output a high voltage on the corresponding gpio pin. reserved all reserved bits must be written as ?0?. 8.7.4 gpio 0 input data register [0xc020] [r] figure 8-45. gpio 0 input data register bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r/w r/w r/w - - - - r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r/w r/w r/w r/w r/w - - - default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpi o12 gpio11 gpio10 gpio9 gpio8 read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r r r r r r r r default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 44 of 82 register description the gpio 0 input data register reads the input data of the gp io pins. the gpio 0 input data register reads from gpio15 to gpio0 while the gpio 1 input data re gister reads from gpio31 to gpio19. every bit represents the vo ltage of that gpio pin. 8.7.5 gpio 1 input data register [0xc026] [r] figure 8-46. gpio 1 input data register register description the gpio 1 input data register reads the input data of the gp io pins. the gpio 0 input data register reads from gpio15 to gpio0 while the gpio 1 input data re gister reads from gpio31 to gpio19. every bit represents the vo ltage of that gpio pin. 8.7.6 gpio 0 direction register [0xc022] [r/w] figure 8-47. gpio 0 direction register register description the gpio 0 direction register controls the direction of the gpio data pins (input/out put). the gpio 0 direction register contro ls gpio15 to gpio0 while the gpio 1 directi on register controls gpio31 to gpio19. when any bit of this register is set to ?1?, the corresponding gp io data pin becomes an output. wh en any bit of this register i s set to ?0?, the corresponding gpio data pin becomes an input. reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r r r - - - - r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r r r r r - - - default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 45 of 82 8.7.7 gpio 1 direction register [0xc028] [r/w] figure 8-48. gpio 1 direction register register description the gpio 1 direction register controls the direction of the gpio data pins (input/out put). the gpio 0 direction register contro ls gpio15 to gpio0 while the gpio 1 directi on register controls gpio31 to gpio19. when any bit of this register is set to ?1?, the corresponding gp io data pin becomes an output. wh en any bit of this register i s set to ?0?, the corresponding gpio data pin becomes an input. reserved all reserved bits must be written as ?0?. 8.8 hss registers there are eight registers dedicated to hss operation. each of these registers are covered in this section and summarized in figure 8-49 . 8.8.1 hss control register [0xc070] [r/w] figure 8-50. hss control register bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 figure 8-49. hss registers register name address r/w hss control register 0xc070 r/w hss baud rate register 0xc072 r/w hss transmit gap register 0xc074 r/w hss data register 0xc076 r/w hss receive address register 0xc078 r/w hss receive length register 0xc07a r/w hss transmit address register 0xc07c r/w hss transmit length register 0xc07e r/w bit # 15 14 13 12 11 10 9 8 field hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive interrupt enable done interrupt enable read/write r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit done interrupt enable receive done interrupt enable one stop bit transmit ready packet mode select receive overflow flag receive packet ready flag receive ready flag read/write r/w r/w r/w r r/w r/w r r default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 46 of 82 register description the hss control register pr ovides high-level status and control over the hss port. hss enable (bit 15) the hss enable bit enables or disables hss operation. 1: enables hss operation 0: disables hss operation rts polarity select (bit 14) the rts polarity select bit selects the polarity of rts. 1: rts is true when low 0: rts is true when high cts polarity select (bit 13) the cts polarity select bit selects the polarity of cts. 1: cts is true when low 0: cts is true when high xoff (bit 12) the xoff bit is a read only bit that indicates if an xoff has been received. this bit is automatically cleared when an xon has been received. 1: xoff received 0: xon received xoff enable (bit 11) the xoff enable bit enables or disables xon/xoff software handshaking. 1: enable xon/xoff software handshaking 0: disable xon/xoff software handshaking cts enable (bit 10) the cts enable bit enables or disables cts/rts hardware handshaking. 1: enable cts/rts hardware handshaking 0: disable cts/rts hardware handshaking receive interrupt enable (bit 9) the receive interrupt enable bit enables or disables the receive ready and receive packet ready interrupts. 1: enable the receive ready and receive packet ready interrupts 0: disable the receive ready and receive packet ready interrupts done interrupt enable (bit 8) the done interrupt enable bit enables or disables the transmit done and receive done interrupts. 1: enable the transmit done and receive done interrupts 0: disable the transmit done and receive done interrupts transmit done interrupt flag (bit 7) the transmit done interrupt flag bit indicates the status of the transmit done interrupt. it will set when a block transmit is finished. to clear the interrupt, a ?1? must be written to this bit. 1: interrupt triggered 0: interrupt did not trigger receive done interrupt flag (bit 6) the receive done interrupt flag bit indicates the status of the receive done interrupt. it will set when a block transmit is finished. to clear the interrupt, a ?1? must be written to this bit. 1: interrupt triggered 0: interrupt did not trigger one stop bit (bit 5) the one stop bit bit selects between one and two stop bits for transmit byte mode. in receive mode, the number of stop bits may vary and does not need to be fixed. 1: one stop bit 0: two stop bits transmit ready (bit 4) the transmit ready bit is a read only bit that indicates if the hss transmit fifo is ready for the cpu to load new data for transmission. 1: hss transmit fifo ready for loading 0: hss transmit fifo not ready for loading packet mode select (bit 3) the packet mode select bit se lects between receive packet ready and receive ready as the interrupt source for the rxintr interrupt. 1: selects receive packet ready as the source 0: selects receive ready as the source receive overflow flag (bit 2) the receive overflow flag bit indicates if the receive fifo overflowed when set. this flag can be cleared by writing a ?1? to this bit. 1: overflow occurred 0: overflow did not occur receive packet ready flag (bit 1) the receive packet ready flag bit is a read only bit that indicates if the hss receive fifo is full with eight bytes or not. 1: hss receive fifo is full 0: hss receive fifo is not full receive ready flag (bit 0) the receive ready flag is a read only bit that indicates if the hss receive fifo is empty or not. 1: hss receive fifo is not empty (one or more bytes is reading for reading) 0: hss receive fifo is empty
CY7C67200 document #: 38-08014 rev. *f page 47 of 82 8.8.2 hss baud rate register [0xc072] [r/w] figure 8-51. hss baud rate register register description the hss baud rate register sets the hss baud rate. at reset, the default value is 0x0017 which sets the baud rate to 2.0 mhz. baud (bits [12:0]) the baud field is the baud rate divisor minus one, in units of 1/48 mhz. therefore the baud rate = 48 mhz/(baud + 1). this puts a constraint on the baud value as follows: (24 ? 1) baud (5000 ? 1) reserved all reserved bits must bit written as ?0?. 8.8.3 hss transmit gap register [0xc074] [r/w] figure 8-52. hss transmit gap register register description the hss transmit gap register is only valid in block transmit mo de. it allows for a programmable number of stop bits to be inse rted thus overwriting the one stop bit in the h ss control register. the default reset value of this register is 0x0009, equivalent t o two stop bits. transmit gap select (bits [7:0]) the transmit gap select field sets the inactive time between tr ansmitted bytes. the inactive time = (transmit gap select ? 7) * bit time. therefore an transmit gap select value of 8 is equal to having one stop bit. reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved baud... read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...baud read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 1 1 1 bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit gap select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 0 0 1
CY7C67200 document #: 38-08014 rev. *f page 48 of 82 8.8.4 hss data register [0xc076] [r/w] figure 8-53. hss data register register description the hss data register contains data received on the hss port (not for block receive mode) when read. this receive data is valid when the receive ready bit of the hss control register is set to ?1?. writing to this register initiates a single byte transfer of data. the transmit ready flag in the hss control register must read ?1? befor e writing to this register (this avoids disrupting the previous/current transmission). data (bits [7:0]) the data field contains the data received or to be transmitted on the hss port. reserved all reserved bits must be written as ?0?. 8.8.5 hss receive address register [0xc078] [r/w] figure 8-54. hss receive address register register description the hss receive address register is used as the base poi nter address for the next hss block receive transfer. address (bits [15:0]) the address field sets the base pointer address for the next hss block receive transfer. 8.8.6 hss receive counter register [0xc07a] [r/w] figure 8-55. hss receive counter register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 49 of 82 register description the hss receive counter register designates the block byte le ngth for the next hss receive transfer. this register must be loaded with the word count minus one to start the block receive tran sfer. as each byte is received this register value is decre - mented. when read, this register indicates the remaining length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved all reserved bits must be written as ?0?. 8.8.7 hss transmit address register [0xc07c] [r/w] figure 8-56. hss transmit address register register description the hss transmit address register is used as the base pointer address for the next hss block transmit transfer. address (bits [15:0]) the address field sets the base pointer address for the next hss block transmit transfer. 8.8.8 hss transmit counter register [0xc07e] [r/w] figure 8-57. hss transmit counter register register description the hss transmit counter register designates the block byte leng th for the next hss transmit tr ansfer. this register must be loaded with the word count minus one to start the block transmit transfer. as each byte is transmitted this register value is decremented. when read, this register indi cates the remaining length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 50 of 82 8.9 hpi registers there are five registers dedicated to hpi operation. in addition , there is an hpi status port which can be address over hpi. ea ch of these registers is covered in this section and are summarized in figure 8-58 . 8.9.1 hpi breakpoint register [0x0140] [r] figure 8-59. hpi breakpoint register register description the hpi breakpoint register is a special on chip memory lo cation which the external processor can access using normal hpi memory read/write cycles. this register is read only by the cpu but is read/write by the hpi port. the contents of this registe r have the same effect as the breakpoint re gister [0xc014]. this special breakpoint r egister is used by software debuggers which interface through the hpi port instead of the serial port. when the program counter matches the breakpoint address, the int1 27 interrupt triggers. to clear this interrupt, a zero value must be written to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. 8.9.2 interrupt routing register [0x0142] [r] figure 8-60. interrupt routing register register description the interrupt routing register allows the hpi port to take over some or all of the sie interrupt s that usually go to the on-chi p cpu. this register is read only by the cpu but is read/write by the hpi port. by setting the appropriate bit to ?1?, the sie interru pt is routed to the hpi port to become the hpi_intr signal and also re adable in the hpi status register . the bits in this register se lect where the interrupts are routed. the i ndividual interrupt enable is handled in the sie interrupt enable register. figure 8-58. hpi registers register name address r/w hpi breakpoint register 0x0140 r interrupt routing register 0x0142 r sie1msg register 0x0144 w sie2msg register 0x0148 w hpi mailbox register 0xc0c6 r/w bit # 15 14 13 12 11 10 9 8 field address... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable read/write r r r r r r r r default 0 00101 0 0 bit # 7 6 5 4 3 2 1 0 field resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable read/write - - - - - - - - default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 51 of 82 vbus to hpi enable (bit 15) the vbus to hpi enable bit routes the otg vbus interrupt to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port id to hpi enable (bit 14) the id to hpi enable bit routes the otg id interrupt to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port sof/eop2 to hpi enable (bit 13) the sof/eop2 to hpi enable bit routes the sof/eop2 interrupt to the hpi port. 1: route signal to hpi port 0: do not route signal to hpi port sof/eop2 to cpu enable (bit 12) the sof/eop2 to cpu enable bit routes the sof/eop2 interrupt to the on-chip cp u. since the sof/eop2 interrupt can be routed to both the on-chip cpu and the hpi port the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu sof/eop1 to hpi enable (bit 11) the sof/eop1 to hpi enable bit routes the sof/eop1 interrupt to the hpi port. 1: route signal to hpi port 0: do not route signal to hpi port
CY7C67200 document #: 38-08014 rev. *f page 52 of 82 sof/eop1 to cpu enable (bit 10) the sof/eop1 to cpu enable bit routes the sof/eop1 interrupt to the on-chip cp u. since the sof/eop1 interrupt can be routed to both the on-chip cpu and the hpi port the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu reset2 to hpi enable (bit 9) the reset2 to hpi enable bit routes the us b reset interrupt that occurs on device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 1 enable (bit 8) both hpi swap bits (bits 8 and 0) must be set to identical va lues. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least signific ant byte goes to hpi_d[7:0]. th is is the default setting. by setting to ?11?, the most signif icant data byte goes to hpi_d[7:0] and the le ast significant byte goes to hpi_d[15:8]. resume2 to hpi enable (bit 7) the resume2 to hpi enable bit routes the usb resume interrupt that occurs on host 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port resume1 to hpi enable (bit 6) the resume1 to hpi enable bit routes the usb resume interrupt that occurs on host 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done2 to hpi enable (bit 3) the done2 to hpi enable bit routes the done interrupt for host/device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done1 to hpi enable (bit 2) the done1 to hpi enable bit routes the done interrupt for host/device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port reset1 to hpi enable (bit 1) the reset1 to hpi enable bit routes the us b reset interrupt that occurs on device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 0 enable (bit 0) both hpi swap bits (bits 8 and 0) must be set to identical va lues. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least signific ant byte goes to hpi_d[7:0]. th is is the default setting. by setting to ?11?, the most signif icant data byte goes to hpi_d[7:0] and the le ast significant byte goes to hpi_d[15:8].
CY7C67200 document #: 38-08014 rev. *f page 53 of 82 8.9.3 siexmsg register [w] ? sie1msg register 0x0144 ? sie2msg register 0x0148 figure 8-61. siexmsg register register description the siexmsg register allows an interrupt to be generated on the hpi port. any write to this regi ster causes the siexmsg flag in the hpi status port to go high and also causes an interrupt on the hp i_intr pin. the siexmsg fl ag is automatically cleared when the hpi port reads from this register. data (bits [15:0]) the data field[15:0] simply needs to have any value written to it to cause siexmsg flag in the hpi status port to go high. 8.9.4 hpi mailbox register [0xc0c6] [r/w] figure 8-62. hpi mailbox register register description the hpi mailbox register provides a common mailbox between the CY7C67200 and the external host processor. if enabled, the hpi mailbox rx full interrupt triggers when the external host processor writes to this register. when the CY7C67200 reads this register the hpi mailbox rx full interrupt automatically gets cleared. if enabled, the hpi mailbox tx empty interrupt triggers when the ex ternal host processor reads from this register. the hpi mail box tx empty interrupt is automatically cleared when the CY7C67200 writes to this register. in addition, when the CY7C67200 writes to this register, th e hpi_intr signal on the hpi port asserts signaling the external processor that there is data in the mailbox to read. the hpi_ intr signal de-asserts when the external host processor reads from this register. message (bits [15:0]) the message field contains the message that the host processor wrote to the hpi mailbox register. bit # 15 14 13 12 11 10 9 8 field data... read/write w w w w w w w w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...data read/write w w w w w w w w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field message... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...message read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 54 of 82 8.9.5 hpi status port [] [hpi: r] figure 8-63. hpi status port register description the hpi status port provides t he external host processor with the mailbox status bits plus several sie status bits. this regist er is not accessible from the on-chip cpu. the additional sie stat us bits are provided to aid external device driver firmware development, and are not recommended for applications that do not have an intimate relationship with the on-chip bios. reading from the hpi status port does not result in a cpu hpi interface memory a ccess cycle. the external host may continu- ously poll this register without d egrading the cpu or dma performance. vbus flag (bit 15) the vbus flag bit is a read only bit that indicates whether otg vbus is greater than 4.4v. after turning on vbus, firmware should wait at least 10 s before this reading this bit. 1: otg vbus is greater then 4.4v 0: otg vbus is less then 4.4v id flag (bit 14) the id flag bit is a read only bit that indicates the state of the otg id pin. sof/eop2 flag (bit 12) the sof/eop2 flag bit is a read only bit that indicates if a sof/eop interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop1 flag (bit 10) the sof/eop1 flag bit is a read only bit that indicates if a sof/eop interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger reset2 flag (bit 9) the reset2 flag bit is a read only bit that indicates if a usb reset interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger mailbox in flag (bit 8) the mailbox in flag bit is a read only bit that indicates if a message is ready in the incoming mailbox. this interrupt clears when on chip cpu reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger bit # 15 14 13 12 11 10 9 8 field vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag read/write r r - r - r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag read/write r r r r r r r r default x x x x x x x x
CY7C67200 document #: 38-08014 rev. *f page 55 of 82 resume2 flag (bit 7) the resume2 flag bit is a read only bit that indicates if a usb resume interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger resume1 flag (bit 6) the resume1 flag bit is a read only bit that indicates if a usb resume interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger sie2msg (bit 5) the sie2msg flag bit is a read only bit that indicates if t he CY7C67200 cpu has written to the sie2msg register. this bit is cleared on an hpi read. 1: the sie2msg register has been written by the CY7C67200 cpu 0: the sie2msg register has not been written by the CY7C67200 cpu sie1msg (bit 4) the sie1msg flag bit is a read only bit that indicates if t he CY7C67200 cpu has written to the sie1msg register. this bit is cleared on an hpi read. 1: the sie1msg register has been written by the CY7C67200 cpu 0: the sie1msg register has not been written by the CY7C67200 cpu done2 flag (bit 3) in host mode the done2 flag bit is a read only bit that indicates if a host packet done interrupt occurs on host 2. in device m ode this read only bit indicates if an any of the endpoint interrupts occurs on device 2. firmware needs to determine which endpoin t interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger done1 flag (bit 2) in host mode the done 1 flag bit is a read only bit that indicate s if a host packet done interrupt occurs on host 1. in device mode this read only bit indicates if an any of the endpoint interrupts occurs on device 1. firmware needs to determine which endpoin t interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger reset1 flag (bit 1) the reset1 flag bit is a read only bit that indicates if a usb reset interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger mailbox out flag (bit 0) the mailbox out flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. this interrupt clears when the external host reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger
CY7C67200 document #: 38-08014 rev. *f page 56 of 82 8.10 spi registers there are 12 registers dedicated to spi operation. each register is covered in this section and summarized in figure 8-64 . 8.10.1 spi configuration register [0xc0c8] [r/w] figure 8-65. spi configuration register register description the spi configuration register controls the spi port. fields apply to both master and slave mode unless otherwise noted. 3wire enable (bit 15) the 3wire enable bit indicates if the miso and mosi data lines are tied together allo wing only half duplex operation. 1: miso and mosi data lines are tied together 0: normal miso and mosi full du plex operation (not tied together) phase select (bit 14) the phase select bit selects advanced or delayed sc k phase. this field only applies to master mode. 1: advanced sck phase 0: delayed sck phase sck polarity select (bit 13) this sck polarity select bit selects the polarity of sck. 1: positive sck polarity 0: negative sck polarity figure 8-64. spi registers register name address r/w spi configuration register 0xc0c8 r/w spi control register 0xc0ca r/w spi interrupt enable register 0xc0cc r/w spi status register 0xc0ce r spi interrupt clear register 0xc0d0 w spi crc control register 0xc0d2 r/w spi crc value 0xc0d4 r/w spi data register 0xc0d6 r/w spi transmit address register 0xc0d8 r/w spi transmit count register 0xc0da r/w spi receive address register 0xc0dc r/w spi receive count register 0xc0de r/w bit # 15 14 13 12 11 10 9 8 field 3wire enable phase select sck polarity select scale select reserved read/write r/w r/w r/w r/w r/w r/w r/w - default 1 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field master active enable master enable ss enable ss delay select read/write r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 1 1 1
CY7C67200 document #: 38-08014 rev. *f page 57 of 82 scale select (bits [12:9]) the scale select field provides control over the sck frequency, based on 48 mhz. see table 8-9 for a definition of this field. this field only applies to master mode. master active enable (bit 7) the master active enable bit is a read only bit that indicates if the master state machine is active or idle. this field only a pplies to master mode. 1: master state machine is active 0: master state machine is idle master enable (bit 6) the master enable bit sets the spi interfac e to master or slave. this bit is only writable when the master active enable bit re ads ?0?, otherwise value will not change. 1: master spi interface 0: slave spi interface ss enable (bit 5) the ss enable bit enables or disables the master ss output. 1: enable master ss output 0: disable master ss output (three-state master ss output, for single ss line in slave mode) ss delay select (bits [4:0]) when the ss delay select field is set to ?00000? this indicate s manual mode. in manual mode ss is controlled by the ss manual bit of the spi control register. when the ss delay select field is set between ?00001? to ?11111?, this value indicates the cou nt in half bit times of auto transfer delay for: ss low to sck active , sck inactive to ss high, ss high time. this field only applies to master mode. table 8-9. scale select fiel d definition for sck frequency scale select [12:9] sck frequency 0000 12 mhz 0001 8 mhz 0010 6 mhz 0011 4 mhz 0100 3 mhz 0101 2 mhz 0110 1.5 mhz 0111 1 mhz 1000 750 khz 1001 500 khz 1010 375 khz 1011 250 khz 1100 375 khz 1101 250 khz 1110 375 khz 1111 250 khz
CY7C67200 document #: 38-08014 rev. *f page 58 of 82 8.10.2 spi control register [0xc0ca] [r/w] figure 8-66. spi control register register description the spi control register cont rols the spi port. fields apply to both master and slave mode unless otherwise noted. sck strobe (bit 15) the sck strobe bit starts the sck strobe at the selected frequency and polarity (set in the spi configuration register), but no t phase. this bit feature can only be enabled when in master mode and must be during a period of inactivity. this bit is self cle aring. 1: sck strobe enable 0: no function fifo init (bit 14) the fifo init bit initializes the fifo and clear the fifo error status bit. this bit is self clearing. 1: fifo init enable 0: no function byte mode (bit 13) the byte mode bit selects between pio (b yte mode) and dma (block mode) operation. 1: set pio (byte mode) operation 0: set dma (block mode) operation full duplex (bit 12) the full duplex bit selects between full duplex and half duplex operation. 1: enable full duplex. full duplex is not allowed and will not set if the 3wire enable bit of the spi configuration register is s et to ?1? 0: enable half duplex operation ss manual (bit 11) the ss manual bit activates or deactivates ss if the ss delay sele ct field of the spi control regi ster is all zeros and is conf igured as master interface. this fi eld only applies to master mode. 1: activate ss, master drives ss line asserted low 0: deactivate ss, master dr ives ss line deasserted high read enable (bit 10) the read enable bit initiates a read phase for a master mode transfer or set the slave to receive (in slave mode). 1: initiates a read phase for a master transfer or sets a slave to receive. in master mode this bit is sticky and remains set unt il the read transfer begins. 0: initiates the write phase for slave operation transmit ready (bit 9) the transmit ready bit is a read only bit that indicates if the transmit port is ready to empty and ready to be written. 1: ready for data to be written to the port. the transmit fifo is not full. 0: not ready for data to be written to the port bit # 15 14 13 12 11 10 9 8 field sck strobe fifo init byte mode full duplex ss manual read enable transmit ready receive data ready read/write w w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field transmit empty receive full transmit bit length receive bit length read/write r r r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 59 of 82 receive data ready (bit 8) the receive data ready bit is a read only bit that indicates if the receive port has data ready. 1: receive port has data ready to read 0: receive port does not have data ready transmit empty (bit 7) the transmit empty bit is a read only bit that indicates if the transmit fifo is empty. 1: transmit fifo is empty 0: transmit fifo is not empty receive full (bit 6) the receive full bit is a read only bit that indicates if the receive fifo is full. 1: receive fifo is full 0: receive fifo is not full transmit bit length (bits [5:3]) the transmit bit length field controls whether a full byte or partial byte is to be transmitted. if transmit bit length is ?000 ?, a full byte is transmitted. if transmit bit length is ?001? to ?111?, the value indicates the number of bits that will be transmitted. receive bit length (bits [2:0]) the receive bit length field controls whether a full byte or pa rtial byte will be received. if receive bit length is ?000? then a full byte will be received. if receive bit length is ?001? to ?111?, then the value indicates the num ber of bits that will be receiv ed. 8.10.3 spi interrupt enable register [0xc0cc] [r/w] figure 8-67. spi interrupt enable register register description the spi interrupt enable regi ster controls the spi port. receive interrupt enable (bit 2) the receive interrupt enable bit enables or disa bles the byte mode receive interrupt (rxintval). 1: enable byte mode receive interrupt 0: disable byte mode receive interrupt transmit interrupt enable (bit 1) the transmit interrupt enable bit enables or disa bles the byte mode transmit interrupt (txintval). 1: enables byte mode transmit interrupt 0: disables byte mode transmit interrupt transfer interrupt enable (bit 0) the transfer interrupt enable bit enables or dis ables the block mode interrupt (xfrblkintval). 1: enables block mode interrupt 0: disables block mode interrupt bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive interrupt enable transmit interrupt enable transfer interrupt enable read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 60 of 82 reserved all reserved bits must be written as ?0?. 8.10.4 spi status register [0xc0ce] [r] figure 8-68. spi status register register description the spi status register is a read only regi ster that provides status for the spi port. fifo error flag (bit 7) the fifo error flag bit is a read only bit that indicates if a fifo error occurred. when this bit is set to ?1? and the transmi t empty bit of the spi control register is set to ?1?, then a tx fifo underflow has occurr ed. similarly, when set with the receive full bit of the spi control register, a rx fifo overflow has occured.this bit automatically clear when the spi fifo init enable bit of the spi control register is set. 1: indicates fifo error 0: indicates no fifo error receive interrupt flag (bit 2) the receive interrupt flag is a read only bit that indicates if a byte mode receive interrupt has triggered. 1: indicates a byte mode receive interrupt has triggered 0: indicates a byte mode receiv e interrupt has not triggered transmit interrupt flag (bit 1) the transmit interrupt flag is a read only bit that indicates a byte mode transmit interrupt has triggered. 1: indicates a byte mode transmit interrupt has triggered 0: indicates a byte mode transmi t interrupt has not triggered transfer interrupt flag (bit 0) the transfer interrupt flag is a read only bit that indicates a block mode interrupt has triggered. 1: indicates a block mode interrupt has triggered 0: indicates a block mode interrupt has not triggered bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag read/write r - - - - r r r default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 61 of 82 8.10.5 spi interrupt clear register [0xc0d0] [w] figure 8-69. spi interrupt clear register register description the spi interrupt clear register is a writ e-only register that allows the spi transmit and spi transfer interrupts to be cleare d. transmit interrupt clear (bit 1) the transmit interrupt clear bit is a write-only bit that clears the byte mode transmit interrupt. this bit is self clearing. 1: clear the byte mode transmit interrupt 0: no function transfer interrupt clear (bit 0) the transfer interrupt clear bit is a write-only bit that will clear the block mode interrupt. this bit is self clearing. 1: clear the block mode interrupt 0: no function reserved all reserved bits must be written as ?0?. 8.10.6 spi crc control register [0xc0d2] [r/w] figure 8-70. spi crc control register register description the spi crc control register provides control over the crc source and polynomial value. crc mode (bits [15:14) the crcmode field selects the crc polynomial as defined in table 8-10 . bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved transmit interrupt clear transfer interrupt clear read/write - - - - - - w w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field crc mode crc enable crc clear receive crc one in crc zero in crc reserved... read/write r/w r/w r/w r/w r/w r r - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 table 8-10. crc mode definition crcmode [9:8] crc polynomial 00 mmc 16-bit: x^16 + x^12 + x^5 + 1(ccitt standard) 01 crc7 7-bit: x^7+ x^3 + 1 10 mst 16-bit: x^16+ x^15 + x^2 + 1 11 reserved, 16-bit polynomial 1.
CY7C67200 document #: 38-08014 rev. *f page 62 of 82 crc enable (bit 13) the crc enable bit enables or disables the crc operation. 1: enables crc operation 0: disables crc operation crc clear (bit 12) the crc clear bit will clear the crc with a load of all ones. this bit is self clearing and always reads ?0?. 1: clear crc with all ones 0: no function receive crc (bit 11) the receive crc bit determines whether the receive bit stream or the transmit bit stream is used for the crc data input in full duplex mode. this bit is a don?t care in half duplex mode. 1: assigns the receive bit stream 0: assigns the transmit bit stream one in crc (bit 10) the one in crc bit is a read only bit that in dicates if the crc value is all zeros or not. 1: crc value is not all zeros 0: crc value is all zeros zero in crc (bit 9) the zero in crc bit is a read only bit that indicates if the crc value is all ones or not. 1: crc value is not all ones 0: crc value is all ones reserved all reserved bits must be written as ?0?. 8.10.7 spi crc value register [0xc0d4] [r/w] figure 8-71. spi crc value register register description the spi crc value register contains the crc value. crc (bits [15:0]) the crc field contains the spi crc. in crc mode crc7, the crc val ue will be a seven bit value [6:0]. therefore bits [15:7] are invalid in crc7 mode. bit # 15 14 13 12 11 10 9 8 field crc... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...crc read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1
CY7C67200 document #: 38-08014 rev. *f page 63 of 82 8.10.8 spi data register [0xc0d6] [r/w] figure 8-72. spi data register register description the spi data register contains data received on the spi port when read. reading it empties the eight byte receive fifo in pio byte mode. this receive data is valid when the receive bit of th e spi interrupt value is set to ?1? (rxintval triggers) or the receive data ready bit of the spi control register is set to ?1?. writi ng to this register in pio byte mode will initiate a transfer of data, the number of bits defined by transmit bit length field in the spi control register. data (bits [7:0]) the data field contains data received or to be transmitted on the spi port. reserved all reserved bits must be written as ?0?. 8.10.9 spi transmit address register [0xc0d8] [r/w] figure 8-73. spi transmit address register register description the spi transmit address register is used as the base address for the spi transmit dma. address (bits [15:0]) the address field sets the base address for the spi transmit dma. 8.10.10 spi transmit count register [0xc0da] [r/w] figure 8-74. spi transmit count register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 64 of 82 register description the spi transmit count register designates the bl ock byte length for the spi transmit dma transfer. count (bits [10:0]) the count field sets the count for the spi transmit dma transfer. reserved all reserved bits must be written as ?0?. 8.10.11 spi receive address register [0xc0dc [r/w] figure 8-75. spi receive address register register description the spi receive address register is issued as the base address for the spi receive dma. address (bits [15:0]) the address field sets the base address for the spi receive dma. 8.10.12 spi receive count register [0xc0de] [r/w] figure 8-76. spi receive count register register description the spi receive count register designates the bl ock byte length for the spi receive dma transfer. count (bits [10:0]) the count field sets the count for the spi receive dma transfer. reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 65 of 82 8.11 uart registers there are three registers dedicated to uart operation. each of these registers is covered in this sect ion and summarized in figure 8-77 . 8.11.1 uart control register [0xc0e0] [r/w] figure 8-78. uart control register register description the uart control register enables or disables the uart allowing gpio7 (uart_txd) and gpio6 (uart_rxd) to be freed up for general use. this register must also be written to set the baud rate, which is based on a 48-mhz clock. scale select (bit 4) the scale select bit acts as a prescaler that will divide the baud rate by eight. 1: enable prescaler 0: disable prescaler baud select (bits [3:1]) refer to table 8-11 for a definition of this field. uart enable (bit 0) the uart enable bit enables or disables the uart. 1: enable uart 0: disable uart. this allows gpio6 and gpio7 to be used for general use figure 8-77. uart registers register name address r/w uart control register 0xc0e0 r/w uart status register 0xc0e2 r uart data register 0xc0e4 r/w bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved scale select baud select uart enable read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 1 1 1 table 8-11. uart baud select definition baud select [3:1] baud rate w/div8 = 0 baud rate w/div8 = 1 000 115.2k baud 14.4k baud 001 57.6k baud 7.2k baud 010 38.4k baud 4.8k baud 011 28.8k baud 3.6k baud 100 19.2k baud 2.4k baud 101 14.4k baud 1.8k baud 110 9.6k baud 1.2k baud 111 7.2k baud 0.9k baud
CY7C67200 document #: 38-08014 rev. *f page 66 of 82 reserved all reserved bits must be written as ?0?. 8.11.2 uart status register [0xc0e2] [r] figure 8-79. uart status register register description the uart status register is a read only register that indicate s the status of the uart buffer. receive full (bit 1) the receive full bit indicates whether the receive buffer is full. it can be programmed to interrupt the cpu as interrupt #5 wh en the buffer is full. this can be done though the uart bit of th e interrupt enable register (0xc 00e). this bit will automatically be cleared when data is read from the uart data register. 1: receive buffer full 0: receive buffer empty transmit full (bit 0) the transmit full bit indicates whether the transmit buffer is full or not. it can be programmed to interrupt the cpu as interr upt #4 when the buffer is empty. this can be done though the uart bit of the interrupt enable register (0xc00e). this bit will automatically be set to ?1? after data is written by ez-host to the uart data register (to be transmitted). this bit will autom atically be cleared to ?0? after the data is transmitted. 1: transmit buffer full (transmit busy) 0: transmit buffer is empty and ready for a new byte of data 8.11.3 uart data register [0xc0e4] [r/w] figure 8-80. uart data register register description the uart data register contains data to be transmitted or received from the uart port. data written to this register will start a data transmission and also causes the uart transmit empty flag of the uart status register to set. when data received on the uart port is read from this register, the uart receive full flag of the uart status register will get cleared. data (bits [7:0]) the data field is where the uart data to be transmitted or received is located reserved all reserved bits must be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive full transmit full read/write - - - - - - r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
CY7C67200 document #: 38-08014 rev. *f page 67 of 82 9.0 pin diagram the following describes the CY7C67200 48-pin fbga. figure 9-1. ez-otg pin diagram 10.0 pin descriptions table 10-1. pin descriptions pin name type description h3 gpio31/sck io gpio31: general purpose io sck: i2c eeprom sck f3 gpio30/sda io gpio30: general purpose io sda: i2c eeprom sda f4 gpio29/otgid io gpio29: general purpose io otgid: input for otg id pin. when used as otgid, this pin must be tied high through an external pull up resistor. assuming v cc = 3.0v, a 10k to 40k resistor must be used. h4 gpio24/int/irq0 io gpio24: general purpose io int: hpi int irq0: interrupt request 0. see register 0xc006. this pin is also one of two possible gpio wakeup sources. g4 gpio23/nrd io gpio23: general purpose io nrd: hpi nrd h5 gpio22/nwr io gpio22: general purpose io nwr: hpi nwr g5 gpio21/ncs io gpio21: general purpose io ncs: hpi ncs h6 gpio20/a1 io gpio20: general purpose io a1: hpi a1 nreset a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 h1 h2 h3 h4 h5 h6 g1 g2 g3 g4 g5 g6 f1 f2 f3 f4 f5 f6 e1 e2 e3 e4 e5 e6 d1 d2 d3 d4 d5 d6 c1 c2 c3 c4 c5 c6 gpio9/d9/ nssi reserved gnd gnd gpio3/d3 gpio1/d1 agnd vcc otgvbus gpio12/d12/ txd gpio13/d13/ rxd gpio14/d14/ rts dp1a gnd avcc boostvcc gpio10/d10/ sck dm1a gpio0/d0 dm2a vswitch boostgnd gpio8/d8/ miso gpio2/d2 gpio11/d1/ mosi dp2a cswitcha cswitchb gpio29/ otgid gpio19/a0 gpio15/d15/ cts/nssi gnd gpio20/a1 gpio22/nwr gpio21/ncs/ nreset gpio24/int/ irq0 gpio23/nrd/ nwait gpio31/scl xtalin gpio4/d4 gpio7/d7/tx vcc vcc gpio6/d6/rx gpio30/sda xtalout gpio5/d5
CY7C67200 document #: 38-08014 rev. *f page 68 of 82 f5 gpio19/a0 io gpio19: general purpose io a0: hpi a0 f6 gpio15/d15/cts/ nssi io gpio15: general purpose io d15: d15 for hpi cts: hss cts nssi: spi nssi e4 gpio14/d14/rts io gpio14: general purpose io d14: d14 for hpi rts: hss rts e5 gpio13/d13/rxd io gpio13: general purpose io d13: d13 for hpi rxd: hss rxd (data is received on this pin) e6 gpio12/d12/txd io gpio12: general purpose io d12: d12 for hpi txd: hss txd (data is transmitted from this pin) d4 gpio11/d11/mosi io gpio11: general purpose io d11: d11 for hpi mosi: spi mosi d5 gpio10/d10/sck io gpio10: general purpose io d10: d10 for hpi sck: spi sck c6 gpio9/d9/nssi io gpio9: general purpose io d9: d9 for hpi nssi: spi nssi c5 gpio8/d8/miso io gpio8: general purpose io d8: d8 for hpi miso: spi miso b5 gpio7/d7/tx io gpio7: general purpose io d7: d7 for hpi tx: uart tx (data is transmitted from this pin) b4 gpio6/d6/rx io gpio6: general purpose io d6: d6 for hpi rx: uart rx (data is received on this pin) c4 gpio5/d5 io gpio5: general purpose io d5: d5 for hpi b3 gpio4/d4 io gpio4: general purpose io d4: d4 for hpi a3 gpio3/d3 io gpio3: general purpose io d3: d3 for hpi c3 gpio2/d2 io gpio2: general purpose io d2: d2 for hpi a2 gpio1/d1 io gpio1: general purpose io d1: d1 for hpi b2 gpio0/d0 io gpio0: general purpose io d0: d0 for hpi f2 dm1a io usb port 1a d? e3 dp1a io usb port 1a d+ c2 dm2a io usb port 2a d? d3 dp2a io usb port 2a d+ g3 xtalin input crystal input or direct clock input g2 xtalout output crystal output . leave floating if direct clock source is used. a5 nreset input reset a6 reserved ? tie to gnd for normal operation . f1 boostv cc power booster power input : 2.7v to 3.6v e2 vswitch analog output booster switching output table 10-1. pin descriptions (continued) pin name type description
CY7C67200 document #: 38-08014 rev. *f page 69 of 82 11.0 absolute maximum ratings this section lists the absolute maximum ratings. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for extended periods can affect device operation and reliability. storage temperature ............................................................................................................ ................................?40c to +125c ambient temperature with power supplied ........................................................................................ ....................?40c to +85c supply voltage to ground potential . .............. .............. .............. .............. .............. ........... ........... ..............................0.0v to +3.6v dc input voltage to any general purpose input pin ... ........................................................................... ................................ 5.5v dc voltage applied to xtalin................................................................................................... .................... ?0.5v to v cc + 0.5v static discharge voltage (per mil-std-883, method 3015) ........................................................................ ..................... > 2000v max output current, per input output. .......................................................................................... ........................................ 4 ma 12.0 operating conditions t a (ambient temperature under bias).............................................................................................. ......................?40c to +85c supply voltage (v cc , av cc ) .............................................................................................................................. ......+3.0v to +3.6v supply voltage (boostv cc ) [5] ............................................................................................................................... ....+2.7v to +3.6v ground voltage ................................................................................................................. .......................................................... 0v f osc (oscillator or crystal frequency) .............................................................................................. ............... 12 mhz 500 ppm ............................................................................................................................... ............................................. parallel resonant 13.0 crystal requirements (xtalin, xtalout) e1 boostgnd ground booster ground c1 otgvbus analog io usb otg vbus d1 cswitcha analog charge pump capacitor d2 cswitchb analog charge pump capacitor g1 av cc power usb power b1 agnd ground usb ground h2, d6, a4 v cc power main vcc g6, b6, a1, h1 gnd ground main ground table 10-1. pin descriptions (continued) pin name type description table 13-1. crystal requirements crystal requirements, (xtalin, xtalout) min. typical max. unit parallel resonant frequency 12 mhz frequency stability ?500 +500 ppm load capacitance 20 33 pf driver level 500 w start-up time 5ms mode of vibration: fundamental note: 5. the on-chip voltage booster circuit boosts boostv cc to provide a nominal 3.3v v cc supply.
CY7C67200 document #: 38-08014 rev. *f page 70 of 82 14.0 dc characteristics table 14-1. dc characteristics [6] parameter description conditions min. typ. max. unit v cc , av cc supply voltage 3.0 3.3 3.6 v boosv cc supply voltage 2.7 3.6 v v ih input high voltage 2.0 5.5 v v il input low voltage 0.8 v i i input leakage current 0< v in < v cc ?10.0 +10.0 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitanc e except d+/d? 10 pf d+/d? 15 pf v hys hysteresis on nreset pin 250 mv i cc [7, 8] supply current 2 transceivers powered 80 100 ma i ccb [7, 8] supply current with booster enabled 2 transceivers powered 135 180 ma i sleep sleep current usb peripheral: includes 1.5k internal pull up 210 500 a without 1.5k internal pull up 5 30 a i sleepb sleep current with booster enabled usb peripheral: includes 1.5k internal pull up 210 500 a without 1.5k internal pull up 5 30 a table 14-2. dc characteristics: charge pump parameter description conditions min. typ. max. unit v a_vbus_out regulated otgvbus voltage 8 ma< i load < 10 ma 4.4 5.25 v t a_vbus_rise v bus rise time i load = 10 ma 100 ms i a_vbus_out maximum load current 8 10 ma c drd_vbus outvbus bypass capacitance 4.4v< v bus < 5.25v 1.0 6.5 pf v a_vbus_lkg otgvbus leakage voltage otgvbus not driven 200 mv v drd_data_lkg dataline leakage voltage 342 mv i charge charge pump current draw i load = 8 ma 20 20 ma i load = 0 ma 0 1 ma i chargeb charge pump current draw with booster active i load = 8 ma 30 45 ma i load = 0 ma 0 5 ma i b_dschg_in b-device (srp capable) discharge current 0v< v bus < 5.25v 8 ma v a_vbus_valid a-device vbus valid 4.4 v v a_sess_valid a-device session valid 0.8 2.0 v v b_sess_valid b-device session valid 0.8 4.0 v notes: 6. all tests were conducted with charge pump off. 7. i cc and i ccb values are the same regardless of usb host or peripheral configuration. 8. there is no appreciable difference in i cc and i ccb values when only one transceiver is powered.
CY7C67200 document #: 38-08014 rev. *f page 71 of 82 14.1 usb transceiver usb 2.0-compatible in full- and low-speed modes. this product was tested as compliant to th e usb-if specification under the test ident ification number (tid) of 100390449 and is listed on the usb-if?s integrators list. 15.0 ac timing characteristics 15.1 reset timing note: 9. clock is 12 mhz nominal. v a_sess_end b-device session end 0.2 0.8 v e efficiency when loaded i load = 8 ma, vcc = 3.3v 75 % r pd data line pull-down 14.25 24.8 r a_bus_in a-device v bus input impedance to gnd v bus is not being driven 40 100 k r b_srp_up b-device v bus srp pull-up pull-up voltage = 3.0v 281 r b_srp_dwn b-device v bus srp pull-down 656 table 14-2. dc characteristics: charge pump (continued) parameter description conditions min. typ. max. unit parameter description min. typ. max. unit t reset nreset pulse width 16 clocks [9] t ioact nreset high to nrd or nwrx active 200 s nreset nrd or nwrl or nwrh t reset t ioact reset timing
CY7C67200 document #: 38-08014 rev. *f page 72 of 82 15.2 clock timing 15.3 i 2 c eeprom timing parameter description min. typ. max. unit f clk clock frequency 12.0 mhz v xinh [10] clock input high (xtalout left floating) 1.5 3.0 3.6 v t clk clock period 83.17 83.33 83.5 ns t high clock high time 36 44 ns t low clock low time 36 44 ns t rise clock rise time 5.0 ns t fall clock fall time 5.0 ns duty cycle 45 55 % xtalin clock timin g t rise t fall t high t clk t low parameter description min. typical max. unit f scl clock frequency 400 khz t low clock pulse width low 1300 ns t high clock pulse width high 600 ns t aa clock low to data out valid 900 ns t buf bus idle before new transmission 1300 ns t hd.sta start hold time 600 ns t su.sta start set-up time 600 ns t hd.dat data in hold time 0 ns t su.dat data in set-up time 100 ns t r input rise time 300 ns t f input fall time 300 ns t su.sto stop set-up time 600 ns t dh data out hold time 0 ns note: 10. v xinh is required to be 3.0 v to obtain an internal 50/50 duty cycle clock. scl t low t high t r t hd.dat t aa t dh sda in sda out 1. i2c eeprom bus timing - serial i/o t su.sta t hd.sta t f t su.dat t buf t su.sto
CY7C67200 document #: 38-08014 rev. *f page 73 of 82 15.4 hpi (host port interface) write cycle timing note: 11. t = system clock period = 1/48 mhz. parameter description min. typical max. unit t asu address set-up ?1 ns t ah address hold ?1 ns t cssu chip select set-up ?1 ns t csh chip select hold ?1 ns t dsu data set-up 6 ns t wdh write data hold 2 ns t wp write pulse width 2 t [11] t cyc write cycle time 6 t [11] ncs nrd nwr addr [1:0] dout [15:0] t asu t wp t ah t cssu t csh t cyc t dsu t wdh
CY7C67200 document #: 38-08014 rev. *f page 74 of 82 15.5 hpi (host port interface) read cycle timing parameter description min. typ. max. unit t asu address set-up ?1 ns t ah address hold ?1 ns t cssu chip select set-up ?1 ns t csh chip select hold ?1 ns t acc data access time, from hpi_nrd falling 1 t [11] t rdh read data hold, relative to the earlier of hpi_nrd rising or hpi_ncs rising 07ns t rp read pulse width 2 t [11] t cyc read cycle time 6 t [11] t asu t rp t ah t cssu t csh t cyc t rdh t acc t rdh ncs nrd nwr addr [1:0] din [15:0]
CY7C67200 document #: 38-08014 rev. *f page 75 of 82 15.6 hss byte mode transmit qt_clk, cpu_a, cpuhss_cs, cpu_wr are internal signals, include d in the diagram to illustrate relationship between cpu opera- tions and hss port operations. bit 0 is lsb of data byte. data bits are high true: hss_txd high = data bit value ?1?. bt = bit time = 1/baud rate. 15.7 hss block mode transmit block mode transmit timing is similar to byte mode, except the stop bit time is controlled by the hss_gap value. the block mode stop bit time, t gap = (hss_gap ? 9) bt, where bt is the bit time, and hss_gap is the content of the hss transmit gap register 90xc074]. the default t gap is 2 bt. bt = bit time = 1/baud rate. 15.8 hss byte and block mode receive receive data arrives asynchronously relative to the internal clock. incoming data bit rate may deviate from the programmed baud rate clock by as much as 5% (with hss_rate value of 23 or higher). byte mode received bytes are buffered in a fifo. the fifo not empty condition becomes the rxrdy flag. block mode received bytes are written directly to the memory system. bit 0 is lsb of data byte. data bits are high true: hss_rxd high = data bit value ?1?. bt = bit time = 1/baud rate. cpu may start another byte transmit right after txrdy goes high start of last data bit to txrdy high: 0 min, 4 t max. (t is qt_clk period) txrdy low to start bit delay: 0 min, bt max when starting from idel. for back to back transmit, new start bit begins immediately following previous stop bit. (bt = bit period) bt bt start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 qt_clk cpu_a[2:0] cpuhss_cs cpu_wr txrdy flag hss_txd byte transmit triggered by a cpu write to the hss_txdata register stop bit start bit programmable 1 or 2 stop bits. 1 stop bit shown. hss_txd t gap bt bt +/- 5% start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit hss_rxd bt +/- 5% 10 bt +/- 5% received byte added to receive fifo during the final data bit time
CY7C67200 document #: 38-08014 rev. *f page 76 of 82 15.9 hardware cts/rts handshake t ctsset-up : hss_cts set-up time before hss_rts = 1.5t min. t ctshold : hss_cts hold time after start bit = 0 ns min. t = 1/48 mhz. when rts/cts hardware handshake is enabled, transmission can be held off by deasserting hss_cts at least 1.5t before hss_rts. transmission resumes w hen hss_cts returns high . hss_cts must remain high until start bit. hss_rts is deasserted in the third data bit time. an application may choose to hold hss_cts until hss_rts is deasserted, which always occurs after the start bit. tctssetup tctssetup start of transmission delayed until hss_cts goes high start of transmission not delayed by hss_cts tctshold tctshold hss_rts hss_cts hss_txd
CY7C67200 document #: 38-08014 rev. *f page 77 of 82 16.0 register summary table 16-1. register summary r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low r 0x0140 hpi breakpoint address... 0000 0000 ...address 0000 0000 r 0x0142 interrupt routing vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable 0001 0100 resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable 0000 0000 w 1: 0x0144 2: 0x0148 siexmsg data... xxxx xxxx ...data xxxx xxxx r/w 0x02n0 device n endpoint n control reserved xxxx xxxx in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable xxxx xxxx r/w 0x02n2 device n endpoint n address address... xxxx xxxx ...address xxxx xxxx r.w 0x02n4 device n endpoint n count reserved count... xxxx xxxx ...count xxxx xxxx r/w 0x02n6 device n endpoint n status reserved overflow flag underflow flag out exception flag in exception flag xxxx xxxx stall flag nak flag length exception flag set-up flag sequence status timeout flag error flag ack flag xxxx xxxx r/w 0x02n8 device n endpoint n count re- sult result... xxxx xxxx ...result xxxx xxxx r 0xc000 cpu flags reserved... 0000 0000 ...reserved global inter- rupt enable negative flag overflow flag carry flag zero flag 000x xxxx r/w 0xc002 bank address... 0000 0001 ...address reserved 000x xxxx r 0xc004 hardware revision revision... xxxx xxxx ...revision xxxx xxxx r/w 0xc006 gpio control write protect enable ud reserved sas enable mode select 0000 0000 hss enable reserved spi enable reserved interrupt 0 polarity select interrupt 0 enable 0000 0000 r/w 0xc008 cpu speed reserved... 0000 0000 .reserved cpu speed 0000 000f r/w 0xc00a power control reserved host/device 2 wake enable reserved host/device 1 wake enable otg wake enable reserved hss wake enable spi wake enable 0000 0000 hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable 0000 0000 r/w 0xc00c watchdog timer reserved... 0000 0000 ...reserved timeout flag period select lock enable wdt enable reset strobe 0000 0000 r/w 0xc00e interrupt enable reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable 0000 0000 hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable 0001 0000 r/w 0xc098 otg control reserved vbus pull-up enable receive disable charge pump enable vbus dis- charge enable d+ pull-up enable d- pull-up enable 0000 0000 d+ pull-down enable d- pull-down enable reserved otg data sta- tus id status vbus valid flag 0000 0xxx r/w 0: 0xc010 1: 0xc012 timer n count... 1111 1111 ...count 1111 1111 r/w 0xc014 breakpoint address... 0000 0000 ...address 0000 0000 r/w 1: 0xc018 2: 0xc01a extended page n map address... ...address r/w 0xc01e gpio 0 output data gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r 0xc020 gpio 0 input data gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r/w 0xc022 gpio 0 direction gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r/w 0xc024 gpio 1 output data gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000
CY7C67200 document #: 38-08014 rev. *f page 78 of 82 r 0xc026 gpio 1 input data gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000 r/w 0xc028 gpio 1 direction gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000 r/w 0xc03c usb diagnostic reserved port 2a diag- nostic enable reserved port 1a diag- nostic enable reserved... 0000 0000 ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select 0000 0000 r/w 0xc070 hss control hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive inter- rupt enable done interrupt enable 0000 0000 transmit done interrupt flag receive done interrupt flag one stop bit transmit ready packet mode select receive overflow flag receive pack- et ready flag receive ready flag 0000 0000 r/w 0xc072 hss baud rate reserved hss baud... 0000 0000 ...baud 0001 0111 r/w 0xc074 hss transmit gap reserved 0000 0000 transmit gap select 0000 1001 r/w 0xc076 hss data reserved xxxx xxxx data xxxx xxxx r/w 0xc078 hss receive address address... 0000 0000 ...address 0000 0000 r/w 0xc07a hss receive counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc07c hss transmit address address.. 0000 0000 ...address 0000 0000 r/w 0xc07e hss transmit counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc080 0xc0a0 host n control reserved 0000 0000 preamble enable sequence select sync enable iso enable reserved arm enable 0000 0000 r/w 0xc082 0xc0a2 host n address address... 0000 0000 ...address 0000 0000 r/w 0xc084 0xc0a4 host n count reserved port select reserved count... 0000 0000 ...count 0000 0000 r 0xc086 0xc0a6 host n pid reserved overflow flag underflow flag reserved 0000 0000 stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag 0000 0000 w 0xc086 0xc0a4 host n ep status reserved 0000 0000 pid select endpoint select 0000 0000 r 0xc088 0xc0a8 host n count result result... 0000 0000 ...result 0000 0000 w 0xc088 0xc0a8 host n device address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc08a 0xc0aa usb n control reserved port a d+ status port a d- status reserved loa mode select reserved xxxx 0000 port a resistors enable reserved port a force d+/- state suspend enable reserved port a sof/eop enable 0000 0000 r/w 0xc08c host 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 reserved port a wake interrupt enable reserved port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 r/w 0xc08c device 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop timeout inter- rupt enable reserved sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc08e 0xc0ae device n address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc090 host 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved xxxx xxxx reserved port a wake interrupt flag reserved port a con- nect change interrupt flag reserved port a se0 status reserved done interrupt flag xxxx xxxx table 16-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
CY7C67200 document #: 38-08014 rev. *f page 79 of 82 r/w 0xc090 device 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc092 0xc0b2 host n sof/eop count reserved count... 0010 1110 ...count 1110 0000 r 0xc092 0xc0b2 device n frame number sof/eop timeout flag sof/eop timeout interrupt count reserved frame... 0000 0000 ...frame 0000 0000 r 0xc094 0xc0b4 host n sof/eop counter reserved counter... ...counter w 0xc094 0xc0b4 device n sof/eop count reserved count... ...count r 0xc096 0xc0b6 host n frame reserved frame... 0000 0000 ...frame 0000 0000 r/w 0xc0ac host 2 interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 reserved port a wake interrupt enable reserved port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 r/w 0xc0ac device 2 interrupt enable reserved sof/eop timeout inter- rupt enable wake interrupt enable sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc0b0 host 2 status reserved sof/eop interrupt flag reserved xxxx xxxx reserved port a wake interrupt flag reserved port a con- nect change interrupt flag reserved port a se0 status reserved done interrupt flag xxxx xxxx r/w 0xc0b0 device 2 status reserved sof/eop timeout interrupt enable wake interrupt flag sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc0c6 hpi mailbox message... 0000 0000 ...message 0000 0000 r/w 0xc0c8 spi configuration 3wire enable phase select sck polarity select scale select reserved 1000 0000 master active enable master enable ss enable ss delay select 0001 1111 r/w 0xc0ca spi control sck strobe fifo init byte mode fullduplex ss manual read enable transmit ready receive data ready 0000 0001 transmit empty receive full transmit bit length receive bit length 1000 0000 r/w 0xc0cc spi interrupt enable reserved... 0000 0000 ...reserved receive inter- rupt enable transmit interrupt enable transfer interrupt enable 0000 0000 r 0xc0ce spi status reserved... 0000 0000 fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag 0000 0000 w 0xc0d0 spi interrupt clear reserved... 0000 0000 ...reserved transmit interrupt clear transmit interrupt clear 0000 0000 r/w 0xc0d2 spi crc control crc mode crc enable crc clear receive crc one in crc zero in crc reserved... 0000 0000 ...reserved 0000 0000 r/w 0xc0d4 spi crc value crc.. 1111 1111 ...crc 1111 1111 r/w 0xc0d6 spi data port t reserved xxxx xxxx data xxxx xxxx r/w 0xc0d8 spi transmit address address... 0000 0000 ...address 0000 0000 r/w 0xc0da spi transmit count reserved count... 0000 0000 ...count 0000 0000 table 16-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
CY7C67200 document #: 38-08014 rev. *f page 80 of 82 r/w 0xc0dc spi receive address address... 0000 0000 ...address 0000 0000 r/w 0xc0de spi receive count reserved count... 0000 0000 ...count 0000 0000 r/w 0xc0e0 uart control reserved... 0000 0000 ...reserved scale select baud select uart enable 0000 0111 r 0xc0e2 uart status reserved... 0000 0000 ...reserved receive full transmit full 0000 0000 r/w 0xc0e4 uart data reserved 0000 0000 data 0000 0000 r hpi status port vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag table 16-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
CY7C67200 document #: 38-08014 rev. *f page 81 of 82 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 17.0 ordering information 18.0 package diagram purchase of i 2 c? components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ez-o tg is a trademark of cypress semiconductor . all product and company names mentioned in this document are trademarks of their respective holders. table 17-1. ordering information ordering code package type temperature range CY7C67200-48bai 48 fbga ?40 to 85c cy3663 development kit g f e d c b a 5 64321 pin 1 corner 5.25 3.75 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b 0.15(4x) 0.210.05 1.20 max. seating plane 0.530.05 0.25 c 0.10 c h e h f g a b c d 6 5 12 3 4 pin 1 corner top view bottom view 7.000.10 7.000.10 a b ?0.05 m c (laser mark) b a c 7.000.10 7.000.10 1.875 2.625 0.36 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48 51-85096-*f
CY7C67200 document #: 38-08014 rev. *f page 82 of 82 document history page document title: CY7C67200 ez-otg? programmab le usb on-the-go host/peripheral controller document number: 38-08014 rev. ecn no. issue date orig. of change description of change ** 111872 03/22/02 mul new data sheet *a 116988 08/23/02 mul preliminary data sheet *b 124954 04/10/03 mul added memory map section and ordering information section moved functional register map tables into register section general clean-up changed from ?preliminary? to ?preliminary confidential? *c 126211 05/23/03 mul added interface description section and power savings and reset section added char data general clean-up removed dram, mdma, and epp added ?programmable? to the title page *d 127334 05/29/03 kkv corrected font to enable correct symbol display *e 129394 10/07/03 mul final data sheet changed memory map section added usb otg logo general clean-up *f 472875 see ecn ari removed ?power consumption? bullet from the features bullet list. corrected number gpio[31:20] to read gpio[31:30] in section 5.13.2 . made sentence into a note in section 6.5 and repeated the note in section 5.8 . corrected the host/device 1 interrupt enable (bit 8) information in section 8.1.6 . corrected data on write protect enable (bit 15) section 8.7.1 to read ?the gpio mode select [15:8] bits are read only until a chip reset?. re-wrote the register description in section 8.9.3 . put document on 2-column template and corrected grammar. put the figure captions at the top of the figures per new template specifications. added static discharge voltage information in section 11.0 added compliance statement and tid in section 14.1 .

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